STEP模块——电子钟
原理
显示时分秒（日期也可以加上），两个按键调节时间
原理图
代码
1 /*-------------------------------------------------------------------------------------- 2 -- Filename ﹕ debounce_module.v 3 -- Author ﹕tony-ning 4 -- Description ﹕按键消抖 5 -- Called by ﹕Top module 6 -- Revision History ﹕15-10-16 7 -- Revision 1.0 8 -- Company ﹕ 9 -- Copyright(c) All right reserved 10 ---------------------------------------------------------------------------------------*/ 11 12 13 module debounce_module 14 ( 15 CLK, //采集时钟，40Hz 16 RSTn, //系统复位信号 17 BUTTON_IN, //按键输入信号 18 BUTTON_OUT //消抖后的输出信号 19 ); 20 input CLK; 21 input RSTn; 22 input BUTTON_IN; 23 output BUTTON_OUT; 24 25 reg key_reg1,key_reg2,key_out; 26 reg [24:0]count2; 27 28 always @( posedge CLK)//CLK 50M 29 begin 30 count2<=count2+1; 31 if(count2==250000) 32 begin 33 key_reg1<=BUTTON_IN; 34 count2<=0; 35 end 36 key_reg2<=key_reg1; 37 key_out<=key_reg2&(!key_reg1); 38 end 39 40 assign BUTTON_OUT = key_out; 41 42 endmodule 43 44 45 46 47 48 49 /* reg [23:0]cnt;//分频计数器 50 reg CLK40HZ;//分频时钟 51 reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q; 52 53 always@(posedge CLK ) //时钟分频 54 begin 55 if(!RSTn) 56 cnt<=0; 57 else if(cnt==24'd312_499) //产生40Hz时钟脉冲 58 begin 59 cnt<=0; 60 CLK40HZ<=~CLK40HZ;//40hz时钟输出 61 end 62 else begin 63 cnt<=cnt+1; 64 end 65 end 66 67 always @(posedge CLK40HZ or negedge RSTn) 68 begin 69 if(~RSTn) 70 begin 71 BUTTON_IN_Q <= 1'b1; 72 BUTTON_IN_2Q <= 1'b1; 73 BUTTON_IN_3Q <= 1'b1; 74 end 75 else 76 begin 77 BUTTON_IN_Q <= BUTTON_IN; 78 BUTTON_IN_2Q <= BUTTON_IN_Q; 79 BUTTON_IN_3Q <= BUTTON_IN_2Q; 80 end 81 end 82 83 wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q; 84 endmodule */ 85 86 /* 87 module debounce_module 88 ( 89 CLK, RSTn, KEY_set,KEY_add,Pin_set, Pin_add 90 ); 91 92 input CLK; 93 input RSTn; 94 input KEY_set; 95 input KEY_add; 96 output Pin_set; 97 output Pin_add; 98 99 reg p=1'b0;//按键状态 100 reg [23:0]cntt; 101 reg k1f1,k1f2;//KEY_set上升沿检测 102 reg k2f1,k2f2;//KEY_add上升沿检测 103 104 105 parameter s_wait=1'b0;//等待按键状态 106 parameter s_delay=1'b1;//按下延时状态 107 108 assign Pin_set=k1f2&!k1f1;//读取按键下降沿 109 assign Pin_add=k2f2&!k2f1; 110 111 112 113 114 115 116 always @ ( posedge CLK or negedge RSTn )//按键消抖状态机 117 if( !RSTn ) 118 begin 119 cntt <= 24'd0; 120 p <= s_wait; 121 end 122 else case(p) 123 s_wait: begin 124 k1f1<=KEY_set;//记录按键值 125 k1f2<=k1f1; 126 127 k2f1<=KEY_add; 128 k2f2<=k2f1; 129 130 if(Pin_set| Pin_add)//当按下，切换到延时并按键只输出一个时钟脉冲 131 begin 132 p<=s_delay; 133 k1f1<=0; 134 k1f2<=0; 135 136 k2f1<=0; 137 k2f2<=0; 138 end 139 end 140 s_delay:if(cntt==24'd249_999) //延时T=10ms 141 begin 142 cntt<=0; 143 p<=s_wait; 144 end 145 else begin 146 cntt<=cntt+1; 147 end 148 149 endcase 150 151 152 153 154 155 156 157 158 159 160 161 162 endmodule */
1 /*-------------------------------------------------------------------------------------- 2 -- Filename ﹕ timer.v 3 -- Author ﹕tony-ning 4 -- Description ﹕timer-based STEP PGGA board 5 -- Called by ﹕-- 6 -- Revision History ﹕15-10-26 7 -- Revision 1.0 8 -- 9 ---------------------------------------------------------------------------------------*/ 10 module timer 11 ( 12 CLK,RSTn,keyset,keyadd,hour1,hour2,min1,min2,sec1,sec2,kstate,CLK2HZ 13 ); 14 15 input CLK; 16 input RSTn; 17 input keyset; 18 input keyadd; 19 output reg[1:0]hour1; 20 output reg[3:0]hour2; 21 output reg[2:0]min1; 22 output reg[3:0]min2; 23 output reg[2:0]sec1; 24 output reg[3:0]sec2; 25 output [1:0]kstate; 26 output reg CLK2HZ; 27 /*-------------------------------define --------------------------------------*/ 28 parameter idle=2'd0;//状态值定义 29 parameter s_hour=2'd1; 30 parameter s_minute=2'd2; 31 parameter s_second=2'd3; 32 33 34 35 reg [27:0]cnt;//分频计数器 36 reg CLK1HZ;//分频时钟 37 reg s_hour_cnt;//小时计数进位状态 38 39 reg[1:0] p; //状态机定义 40 //reg[2:0] p_back; //状态返回 41 42 assign kstate=p; 43 44 always@(posedge CLK ) //时钟分频 45 begin 46 if(!RSTn) 47 cnt<=0; 48 else if(cnt==28'd24_999_999) //产生1Hz时钟脉冲 49 begin 50 cnt<=0; 51 CLK1HZ<=1; 52 CLK2HZ<=~CLK2HZ;//2hz时钟输出 53 //min1<=0; 54 end 55 else begin 56 cnt<=cnt+1; 57 CLK1HZ<=0; 58 //min1<=min1+1; 59 end 60 end 61 62 63 64 always@(posedge CLK )//状态机切换 65 begin 66 if(!RSTn) 67 p<=idle; 68 else 69 case (p) 70 idle: begin 71 if (keyset) 72 p<=s_hour; //next设置小时 73 else p<=idle; 74 /***************************************/ 75 case(s_hour_cnt)//小时计数 76 0: begin 77 if(hour1==2)//10进位情况 78 begin 79 s_hour_cnt<=1; 80 end 81 if(hour2 ==10) 82 begin 83 hour2<=0; 84 hour1<=hour1+1; 85 end 86 //else hour2<=hour2+1; 87 end 88 1: if(hour2==4) 89 begin 90 s_hour_cnt<=0;//4进位情况 91 hour1<=0; 92 hour2<=0; 93 end 94 endcase 95 /***************************************/ 96 if(min1==6) //分钟计数 97 begin 98 min1<=0; 99 hour2<=hour2+1; 100 end 101 else if(min2==10) 102 begin 103 min1<=min1+1; 104 min2<=0; 105 end 106 107 /***************************************/ 108 if(sec1==6) //秒计数 109 begin 110 sec1<=0; 111 min2<=min2+1; 112 end 113 else if(sec2==10) 114 begin 115 sec1<=sec1+1; 116 sec2<=0; 117 end 118 else if(CLK1HZ)//每秒加一 119 sec2<=sec2+1; 120 end 121 s_hour: 122 begin 123 if (keyset) 124 p<=s_minute; //next设置分钟 125 else p<=s_hour; 126 /***************************************/ 127 if(keyadd) //小时数值按键设定 128 begin 129 case(s_hour_cnt)//小时计数 130 0: begin 131 if(hour1==2)//10进位情况 132 begin 133 s_hour_cnt<=1; 134 end 135 if(hour2 ==9) 136 begin 137 hour2<=0; 138 hour1<=hour1+1; 139 end 140 else hour2<=hour2+1; 141 end 142 1: if(hour2==3) 143 begin 144 s_hour_cnt<=0;//4进位情况 145 hour1<=0; 146 hour2<=0; 147 end 148 else hour2<=hour2+1; 149 endcase 150 end 151 end 152 s_minute: 153 begin 154 if (keyset) 155 p<=s_second; //next设置秒 156 else p<=s_minute; 157 158 if(keyadd) //分钟数值按键设定 159 begin 160 if(min1==5 && min2==9) //分钟计数 161 begin 162 min1<=0; 163 min2<=0; 164 hour2<=hour2+1; 165 end 166 else if(min2==9) 167 begin 168 min1<=min1+1; 169 min2<=0; 170 end 171 else min2<=min2+1; 172 end 173 end 174 s_second:begin 175 if (keyset) 176 p<=idle; //next返回正常显示 177 else p<=s_second; 178 179 if(keyadd) //秒数值按键设定 180 begin 181 if(sec1==5 && sec2==9) //秒计数 182 begin 183 sec1<=0; 184 min2<=min2+1; 185 end 186 else if(sec2==9) 187 begin 188 sec1<=sec1+1; 189 sec2<=0; 190 end 191 else sec2<=sec2+1; 192 end 193 end 194 195 endcase 196 end 197 198 199 endmodule 200
1 /*-------------------------------------------------------------------------------------- 2 -- Filename show_ctrl.v 3 -- Author ﹕tony-ning 4 -- Description ﹕数码管显示字符 5 -- Called by ﹕Top module 6 -- Revision History 5-10-16 7 -- Revision 1.0 8 -- Company 9 -- Copyright(c) All right reserved 10 ---------------------------------------------------------------------------------------*/ 11 module show_ctrl 12 ( 13 CLK,RSTn,hour1,hour2,min1,min2,sec1,sec2,kstate,CLK2HZ,lamp4,lamp3,lamp2,lamp1,dualpoint 14 ); 15 16 input CLK,RSTn; 17 input [1:0]hour1; 18 input [3:0]hour2; 19 input [2:0]min1; 20 input [3:0]min2; 21 input [2:0]sec1; 22 input [3:0]sec2; 23 input [1:0]kstate; 24 input CLK2HZ; 25 output reg[6:0]lamp4; 26 output reg[6:0]lamp3; 27 output reg[6:0]lamp2; 28 output reg[6:0]lamp1; 29 30 output reg dualpoint; 31 32 33 ///////////////////////////////////////////////// 34 parameter idle=2'd0; 35 parameter s_hour=2'd1; 36 parameter s_minute=2'd2; 37 parameter s_second=2'd3; 38 39 parameter light=1'b0; 40 parameter dark=1'b1; 41 42 reg [6:0]number[9:0]; 43 44 /////////////////////////////////////////////// 45 initial 46 begin 47 number[0] =7'b0000001; //abcdefg 0 48 number[1] =7'b1001111; //abcdefg 1 49 number[2] =7'b0010010; //abcdefg 2 50 number[3] =7'b0000110; //abcdefg 3 51 number[4] =7'b1001100; //abcdefg 4 52 number[5] =7'b0100100; //abcdefg 5 53 number[6] =7'b0100000; //abcdefg 6 54 number[7] =7'b0001111; //abcdefg 7 55 number[8] =7'b0000000; //abcdefg 8 56 number[9] =7'b0000100; //abcdefg 9 57 number[10]=7'b1111111; //abcdefg null 58 end 59 60 61 62 always@(*) 63 begin 64 case(kstate) 65 idle: begin 66 lamp4<=number[hour1]; 67 lamp3<=number[hour2]; 68 if(CLK2HZ) dualpoint<=light; 69 else dualpoint<=dark; 70 lamp2<=number[min1]; 71 lamp1<=number[min2]; 72 end 73 s_hour: begin 74 75 if(CLK2HZ) 76 begin 77 lamp4<=number[hour1]; 78 lamp3<=number[hour2]; 79 end 80 else 81 begin 82 lamp4<=number[10]; 83 lamp3<=number[10]; 84 end 85 dualpoint<=light; 86 lamp2<=number[min1]; 87 lamp1<=number[min2]; 88 end 89 s_minute: begin 90 lamp4<=number[hour1]; 91 lamp3<=number[hour2]; 92 dualpoint<=light; 93 94 if(CLK2HZ) 95 begin 96 lamp2<=number[min1]; 97 lamp1<=number[min2]; 98 end 99 else 100 begin 101 lamp2<=number[10]; 102 lamp1<=number[10]; 103 end 104 end 105 s_second: begin 106 lamp4<=number[10]; 107 lamp3<=number[10]; 108 dualpoint<=light; 109 110 if(CLK2HZ) 111 begin 112 lamp2<=number[sec1]; 113 lamp1<=number[sec2]; 114 end 115 else 116 begin 117 lamp2<=number[10]; 118 lamp1<=number[10]; 119 end 120 121 end 122 endcase 123 end 124 125 endmodule
1 /*-------------------------------------------------------------------------------------- 2 -- Filename ﹕ top.v 3 -- Author ﹕tony-ning 4 -- Description ﹕top 5 -- Called by ﹕ 6 -- Revision History ﹕15-10-16 7 -- Revision 1.0 8 -- Company ﹕ 9 -- Copyright(c) All right reserved 10 ---------------------------------------------------------------------------------------*/ 11 module top 12 ( 13 CLK,RSTn,KEY_set,KEY_add,lamp4,lamp3,lamp2,lamp1,dualpoint 14 ); 15 16 input CLK; 17 input RSTn; 18 input KEY_set; 19 input KEY_add; 20 output [6:0]lamp4;//数码管 21 output [6:0]lamp3; 22 output [6:0]lamp2; 23 output [6:0]lamp1; 24 output dualpoint; 25 26 wire [1:0]hour1; 27 wire [3:0]hour2; 28 wire [2:0]min1; 29 wire [3:0]min2; 30 wire [2:0]sec1; 31 wire [3:0]sec2; 32 wire [1:0]kstate; 33 wire CLK2HZ; 34 wire Pin_set; 35 wire Pin_add; 36 37 38 39 debounce_module KEYset_debounce 40 ( 41 .CLK(CLK), 42 .RSTn(RSTn), 43 .BUTTON_IN(KEY_set), 44 .BUTTON_OUT(Pin_set) 45 ); 46 47 debounce_module KEYadd_debounce 48 ( 49 .CLK(CLK), 50 .RSTn(RSTn), 51 .BUTTON_IN(KEY_add), 52 .BUTTON_OUT(Pin_add) 53 ); 54 55 timer time_generater 56 ( 57 .CLK(CLK), 58 .RSTn(RSTn), 59 .keyset(Pin_set), 60 .keyadd(Pin_add), 61 .hour1(hour1), 62 .hour2(hour2), 63 .min1(min1), 64 .min2(min2), 65 .sec1(sec1), 66 .sec2(sec2), 67 .kstate(kstate), 68 .CLK2HZ(CLK2HZ) 69 ); 70 71 show_ctrl show_module 72 ( 73 .CLK(CLK), 74 .RSTn(RSTn), 75 .hour1(hour1), 76 .hour2(hour2), 77 .min1(min1), 78 .min2(min2), 79 .sec1(sec1), 80 .sec2(sec2), 81 .kstate(kstate), 82 .CLK2HZ(CLK2HZ), 83 .lamp4(lamp4), 84 .lamp3(lamp3), 85 .lamp2(lamp2), 86 .lamp1(lamp1), 87 .dualpoint(dualpoint) 88 ); 89 90 91 92 endmodule 93
PCB
实物图
