//------------------------------------------------------------------------------
// File : gig_ethernet_pcs_pma_0_johnson_cntr.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
// Description: This logic describes a standard johnson counter to
// create divided down clocks. A divide by 10 clock is
// created.
//
// The capabilities of this Johnson counter are extended
// with the use of the clock enables - it is only the
// clock-enabled cycles which are divided down.
//
// The divide by 10 clock is output directly from a rising
// edge triggered flip-flop (clocked on the input clk).
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// Module declaration.
//-----------------------------------------------------------------------------
module gig_ethernet_pcs_pma_0_johnson_cntr
(
input reset, // Synchronous Reset
input clk, // Input clock (always at 125MHz)
input clk_en, // Clock enable for rising edge triggered flip flops
output clk_div10 // (Clock, gated with clock enable) divide by 10
);
//----------------------------------------------------------------------------
// internal signals used in this top level wrapper.
//----------------------------------------------------------------------------
reg reg1; // first flip flop
reg reg2; // second flip flop
reg reg3; // third flip flop
reg reg4; // fourth flip flop
reg reg5; // fifth flip flop
// Create a 5-stage shift register
always @(posedge clk)
begin
if (reset == 1'b1) begin
reg1 <= 1'b0;
reg2 <= 1'b0;
reg3 <= 1'b0;
reg4 <= 1'b0;
reg5 <= 1'b0;
end
else begin
if (clk_en == 1'b1) begin
if (reg5 == 1'b1 && reg4 == 1'b0) begin // ensure that LFSR self corrects on every repetition
reg1 <= 1'b0;
reg2 <= 1'b0;
reg3 <= 1'b0;
reg4 <= 1'b0;
reg5 <= 1'b0;
end
else begin
reg1 <= !reg5;
reg2 <= reg1;
reg3 <= reg2;
reg4 <= reg3;
reg5 <= reg4;
end
end
end
end
// The 5-stage shift register causes reg3 to toggle every 5 clock
// enabled cycles, effectively creating a divide by 10 clock
assign clk_div10 = reg3;
endmodule
