UltraScale Architecture Clocking Resources

1、UltraScale architecture-based devices contain one CMT per I/O bank. The MMCMs serve as
frequency synthesizers for a wide range of frequencies, and as jitter filters for either
external or internal clocks, and deskew clocks.

2、In UltraScale™ architecture-based devices, the clock management tile (CMT) includes a
mixed-mode clock manager (MMCM) and two phase-locked loops (PLLs). The main purpose
of the PLL is to generate clocking for the I/Os. But it also contains a limited subset of the
MMCM functions that can be used for general clocking purposes.

3、PLLs
There are two PLLs per CMT that provide clocking to the PHY logic and I/Os. In addition,
they can be used as frequency synthesizers for a wide range of frequencies, serve as jitter
filters, and provide basic phase shift capabilities and duty cycle programming. The PLLs
differ from the MMCM in number of outputs, cannot deskew clock nets, and do not have
advanced phase shift capabilities, Multipliers and input dividers have a smaller value range
and do not have many of the other advanced features of the MMCM.
 

4、Clock Buffers
The PHY global clocking contains several sets of BUFGCTRLs, BUFGCEs, and BUFGCE_DIVs.
Each set can be driven by four GC pins from the adjacent bank, MMCMs, PLLs in the same
PHY, and interconnect. The clock buffers then drive the routing and distribution resources
across the entire device. Each PHY contains 24 BUFGCEs, 8 BUFGCTRLs, and 4 BUFGCE_DIVs
but only 24 of them can be used at the same time.
 

5、External global user clocks must be brought into the UltraScale device on differential clock
pin pairs called global clock (GC) inputs. There are four GC pin pairs in each bank that have
direct access to the global clock buffers, MMCMs, and PLLs that are in the CMT adjacent to
the same I/O bank. The UltraScale+ architecture has four HDGC pins per HD I/O bank. HD
I/O banks are only part of the UltraScale+ family. Since HD I/O banks do not have a XIPHY
and CMT next to them, the HDGC pins can only directly drive BUFGCEs (BUFGs) and not
MMCMs/PLLs. Therefore, clocks that are connected to an HDGC pin can only connect to
MMCMs/PLLs through the BUFGCEs. To avoid a design rule check (DRC) error, set the
property CLOCK_DEDICATED_ROUTE = FALSE. GC inputs provide dedicated, high-speed
access to the internal global and regional clock resources. GC inputs use dedicated routing
and must be used for clock inputs where the timing of various clocking features is
imperative. General-purpose I/O with local interconnects should not be used for clock
signals.
Each I/O bank is located in a single clock region and includes 52 I/O pins. Of the 52 I/O pins
in each I/O bank in every I/O column, there are four global clock input pin pairs (a total of
eight pins). Each global clock input:
• Can be connected to a differential or single-ended clock on the PCB.
• Can be configured for any I/O standard, including differential I/O standards.
• Has a P-side (master), and an N-side (slave)