VHDL三输入与门、四选一复用器

1、三输入与门

--定义头文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
 
--定义实体，定义输入和输出
ENTITY A3 IS
	PORT(a,b,c:IN STD_LOGIC;
		  y:OUT STD_LOGIC);
END A3;
 
 
--定义结构体，定义实体内部的逻辑关系
ARCHITECTURE bhv OF A3 IS
 BEGIN
  PROCESS(a,b,c)
   BEGIN
	 IF a='0' AND b='0' AND c='0' THEN
	  y<='0';
	 ELSIF a='0' AND b='0' AND c='1' THEN
	  y<='0';
	 ELSIF a='0' AND b='1' AND c='0' THEN
	  y<='0';
	 ELSIF a='0' AND b='1' AND c='1' THEN
	  y<='0';
	 ELSIF a='1' AND b='0' AND c='0' THEN
	  y<='0';
	 ELSIF a='1' AND b='0' AND c='1' THEN
	  y<='0';
	 ELSIF a='1' AND b='1' AND c='0' THEN
	  y<='0';
	 ELSE
	  y<='1';
	 END IF;
	END PROCESS;
END bhv;

2、四选一复用器

--定义头文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
 
--定义实体，定义输入和输出
ENTITY MUX_41 IS
	PORT(a,b,c,d,s0,s1:IN STD_LOGIC;
		  y:OUT STD_LOGIC);
END MUX_41;
 
 
--定义结构体，定义实体内部的逻辑关系
ARCHITECTURE bhv OF MUX_41 IS
SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0);
 BEGIN
 s<=s1&s0;
  PROCESS(a,b,c,d)
   BEGIN
	 IF s1='0' AND s0='0' THEN
	  y<=a;
	 ELSIF s1='0' AND s0='1' THEN
	  y<=b;
	 ELSIF s1='1' AND s0='0' THEN
	  y<=c;
	 ELSE
	  y<=d;
	 END IF;
	END PROCESS;
END bhv;

参考文献：四选1数据选择器的VHDL程序设计_通信汪的美好生活的博客-CSDN博客