2014年2月12日

when to use define macro vs generate

摘要： Summary: after trying some time to differentiate our design with IFDEFs and Generates, we realized that it is not practical. Now we maintain two source codes in parallel - one for each platform. Use IFDEFs in top modules to remove/switch between modules and remove unnecessary ports and parameter... 阅读全文

posted @ 2014-02-12 15:49 testset 阅读(162) 评论(0) 推荐(0) 编辑

`define marcos usage in system verilog

摘要： Note it is not supported in verilog http://en.wikipedia.org/wiki/SystemVerilogThe preprocessor has improved `define macro-substitution capabilities, specifically substitution within literal-strings (""), as well as concatenation of multiple macro-tokens into a single word.link fromhttps:// 阅读全文

posted @ 2014-02-12 15:40 testset 阅读(1451) 评论(0) 推荐(0) 编辑

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