testset

摘要： The qverilog command compiles (vlog), optimizes (vopt), and simulates (vsim) Verilog andSystemVerilog designs in a single step. It combines the compile, elaborate, and simulate phasestogether, as some users may be accustomed to doing with NC-Sim. This command is providedto ease these users’ transiti 阅读全文

摘要： the simple reason is the uvm_macros.svh not included in the top fileand note: there is no need to add +incdir+ to look for the svhbecause the questa will automatically fix the path when import uvm_pkg ** Error: Environment.sv(16): (qverilog-2163) Macro `uvm_component_utils is undefined.** Error: Env 阅读全文