section 1
摘要：
1. quartus setup 1.1 assignment-->setting 1.2 editor-> sdc file case sensitive2. core timing 2.1 create_clock 2.2 derive_pll_clockcreate_generated_clocktransceiver_clock 2.3 derive_clock_uncertainty 2.4 set_clock_groupsun-relatedoptions -asynchronous,-exclusive ASIC, no matters in FPG... 阅读全文
posted @ 2013-04-07 11:18 testset 阅读(125) 评论(0) 推荐(0) 编辑
