1. -----> D ----> 的周期
| |
|-<- T -<-|
2. sequential -> timing; combinational -> logic;
3. output can not directly use the input signal
4. test 2 if one register, .v .sv case para synthesis ; full; unique case in sv
posted on 2013-06-04 20:16 testset 阅读(100) 评论(0) 编辑 收藏 举报
