SET_MULTICYCLE_PATH .......................................................................................................................................... 80
-from/-rise_from/-fall_from - These options control the source
-to/-rise_to/-fall_to - These options control the destination
values increase, the relationship gets looser, i.e. the setup relationship gets more positive and the hold relationship gets more negative.
-start/-end - matters if the period of the source clock is different than the destination clock.
GET_FANOUTS ......................................................................................................................................................... 83
SET_MAX_DELAY/SET_MIN_DELAY ......................................................................................................................... 84
two constraints act as low-level overrides of the setup and hold relationships. Note that these constraints are not point-to-point requirements between registers, which is a common misperception,
rather than being based on edges of the existing clock, they are based solely on the <value> entered by the user
SET_FALSE_PATH ..................................................................................................................................................... 85
It can be between keepers(registers, I/Os, etc.) or between clocks.
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b] where clock clk_a drives the source register and clock clk_b drives the destination register. Note that transfers in the other direction have not been cut
SET_CLOCK_UNCERTAINTY ..................................................................................................................................... 86
add uncertainty to those perfect edges, and mimic clock-level effects like jitter.
-add option, so their uncertainty is additive to that calculated by derive_clock_uncertainty
does not have its uncertainty propagate to generated clocks downstream
SET_CLOCK_LATENCY ............................................................................................................................................. 86
models board-level clock delays, although admittedly, I seldom see it used.
useful is for I/O constraints, where the user can specify the clock latency to the FPGA clock port, as well as the clock latency to the virtual clock.
second use for set_clock_latency is on feedback clocks, where a clock goes out an FPGA port and then comes back.
-early and -late values are used for internal clocks, and then removed through common clock path pessimism.
set_clock_latency had no affect within the clock domain, and only has an affect when relating to other clocks with different latencies,
SET_INPUT_DELAY/SET_OUTPUT_DELAY ................................................................................................................ 87
two dedicated commands, not think of them as constraints at all. Instead they describe a circuit outside of the FPGA
-clock - This is the clock driving this external register. In almost all cases a virtual clock. for source-synchronous outputs, should be the name of a create_generated_clock applied to the port driving out the clock.
-max value increases, the setup requirement gets tighter because the FPGA's internal delays must get smaller in order to meet the setup relationship between clocks.
-min value decreases, the hold requirement gets tighter, because the FPGA must add more delay in order to meet the hold relationship between clocks.
-reference_pin - This option is for set_output_delay only, and meant to reference the output port that a clock goes out on
-clock_fall - This option states that the external register is clocked on the falling edge of the clock. commonly used on double-data rate interfaces
-add_delay - In reality it means there is another external register connected to the port. commonly used on double-data rate interfaces
SET_MAX_SKEW ...................................................................................................................................................... 89
