Allego Quick Reports
Assigned Function Report
Lists all assigned functions, sorted by function designator.
Bill of Material Report
Lists all components in the design, sorted by reference designator.
Bill of Material [Condensed] Report
Lists all components in the design, sorted by symbol type.
Cadence Schematic Feedback Report
Creates a back-annotation file for a Cadence front-end tool and lists the nets attached to each pin on the board, sorted by component and device type. This report excludes power and ground nets or pins. Originally intended for Design Entry HDL or System Connectivity Manager users, the information is valid for customers using third party logic as well. Obtained from the design file, the four columns are:
- Reference Designator
- Device Type
- Pin
- Net Name
Lists all components in the design, sorted by reference designator.
所有器件信息，包括器件型号、数量值、封装名称、具体的坐标位置
在设计中列出层的名称，它们的类型，材料，厚度，电导率，介电常数和其他参数。 有关详细内容的说明，请参阅报告标题。
Dangling Lines, Via, and Antenna Report
This report shows dangling connect lines, vias and antenna vias in the design. See the report header for detail content description.
本报告显示了设计中的悬挂连接线，通孔和天线通孔。 有关详细内容的说明，请参阅报告标题。Generates a history of partition parameters, including the names and number of partitions, their database status, path, designer, and any notes when you choose to partition a design.
生成分区参数的历史记录，包括分区的名称和数量，数据库状态，路径，设计器和任何注释。
Design Rules Check (DRC)Report
Lists all design rule violations.
Design Rules Net Shorts Check(DRC) Report
Lists all design rule violations for net shorting in the design.
Diffpair Gap Report
Reports gap between nets of differential pair in the design. The report lists nominal gap, actual gap, gap deviation, segment length, segment end points for every differential pair.
报告设计中差分对网络的间距。 报告列出了每个差分对的标称间隙，实际间隙，间隙偏差，段长度，段终点。
Embedded Cavity Report
Embedded Component Report
Lists total etch length on each layer
显示每层总共的走线长度
Lists total etch length on each etch layer for each net.
Etch Length By Layer and Width Report
Lists net name, layer name, and etch length by layer.
Lists net name, etch length by net, etch length, manhattan length, and percent manhattan.
显示所有网络的走线长度，也包含manhatten长度，曼哈顿距离就是DX+DY的距离，就是，两个点连线的两个直角边距离。
Lists net name and etch length by pin pair.
显示网络名及每一个网络的走线长度。
Film Area Report
Lists film name, class, subclass, area, and metal percentage between copper and board-outline (or route keep-in, when board outline is added as lines instead of a shape). While calculating metal percentage, all objects present on the film, irrespective of their location -- they can be located either inside or outside board outline -- are considered.
The metal percentage calculation takes place as follows:
Film Area Short Report
Function Pin Report
Lists all assigned and unassigned function pins, sorted first by function designator, then by pin name.
Function Report
Lists all assigned and unassigned functions, sorted by function designator.
Missing Fillets Report
Lists Pad and T fillet parameters used to generate fillets as well as missing and partial fillets, the latter of which occur when the tool creates a portion of a fillet. You can click on the coordinates in the report to precisely locate missing or partial fillets in the design. Other information includes net name, item, location, and subclass.
Module Report
Lists module instance, module definition, x and y coordinates, angle, and total module count.
Net List Report
Lists connections, sorted first by net name then by pin number.
Net Loop Report
Net Single Pin and No Pin
Lists nets that have only a single pin or no pins attached to them.
Note: The layout editors do not allow nets without any pins, so these nets will not appear in the report.
Note: You can add OK_NET_ONE_PIN property to the net to suppress it from being reported.
Netin Back (back anno.)
Creates a netlist file that you can load or back-annotate. Writes the $FUNCTIONS section by device type, function type, and function designator; writes $NETS section by net name, function designator, and pin name.
Netin (non-back)
Creates a netlist file that you can load. Writes the $PACKAGES section by device type, symbol name, and reference designator; writes $NETS section by net name, reference designator, and pin number.
Padstack Definition Report
Lists all pad definitions in the design.
Padstack Usage Report
Lists symbol pins that use padstack definitions.
Pin Swap Report
Placed Component Report
The Placed Component report lists all placed components, sorted by reference designator. Other information supplied in the report includes:
Properties on Nets Report
Lists properties attached to nets, sorted by net name.
Route Jumper Report
Shape Dynamic State Report
Lists the state of all shapes, either out-of-date or smooth.
Shape Islands Report
Lists all shapes on the net that are not attached.
Shape No Net Report
Lists all etch or conductor shapes that are not assigned to a net.
Shape Report
Lists dynamic shape settings; generation results, including number of dynamic etch shapes and their areas; shape fill type; thermal relief connects; void controls; and clearance settings.
铺铜报告
Slot Hole Report
Details information about oval and rectangularly shaped slot holes for fabrication purposes when you do not want to generate NC Route output. For each slot hole, the report lists the X/Y location of the hole center; the padstack-defined Size X, Size Y, and Plating settings; and the rotation inherited from the symbol using the padstack. Size X and Size Y represent the values at 0 rotation without mirroring.
Spare Function Report
Lists functions available on a placed or unplaced component.
Summary Drawing Report
Lists major statistics of the drawing.
总结出所有的关键信息，经常用该命令，包括是否100%连接，以及是否有daling线，以及所设计单板的pin密度等等。
Symbol Availability Check Report
Lists the library paths of all unplaced symbols.
Symbol Library Path Report
Lists the path to each symbols library of origin.
Symbol Pin Report
Lists all symbol pin instances, sorted first by reference designator, then by pin number. Also reports a pin's X/Y coordinates, symbol name, comp device type, padstack name, and net name.
显示每个器件的每个pin所对应的属性。
Testprep Report
Organizes data regarding the testpoint coverage of a design, highlighting untestable nets, as well as the percentage coverage, number of nets covered, number of testpoints, and number/percentage of testpoints on top/bottom sides.
也是经常用，用来显示所加测试点所占的比例。
Unassigned Functions Report
Lists all unassigned functions, sorted by function designator.
Unconnected Pins Report
Lists all unconnected pins in the design with hyperlinks to X/Y coordinates, net names, and total unconnected pins.
Unplaced Components Report
Lists all unplaced components in the design.
Unused Blind/Buried Via Report
Identifies unused blind and buried vias associated with a via stack structure, which can comprise coincidently placed microvias, blind and buried vias, or a combination of both. For example, consider the via stack Micro1-2, BB2-7, and Micro7-8. If a trace connects to the stack on Layers 3 and 6, Micro1-2 and Micro7-8 are identified as unused. Click on the hyperlink to navigate to their location. Unavailable in Allegro PCB Design L, OrCAD, and Allegro PCB Performance option L.
Lists the third party $SCHEDULE net list.
Via List by Net Report
Lists net name, total vias, through vias, BB vias and via name.
Via List by Net and Layer Report
Lists net name, total vias, through vias, BB vias and via name in each layer.
Waived Design Rules Check Report
Lists all waived design rule violations in the design.
