(转)Altera Forum精彩问答汇总

原文链接：http://group.ednchina.com/56/31122.aspx

 

Altera Forum精彩问答汇总

 

I can't afford losing any of these invaluable information anymore! It is not too late if I start reading and collecting them from now on. I will look the threads through everyday as I do with my Hotmail E-mails and EETimes RSSs.

It's all about Timing：

Sun Nov 01 2009 17:17:32 GMT+0800 signal transfer in different clock domains
Sun Nov 01 2009 16:53:26 GMT+0800 Implementation and Timing of Reset Circuits
Sun Nov 01 2009 16:46:41 GMT+0800 Timequest & Output delay problem "I've found it easy to totally get wrapped up into equations and lost in the details."
Sun Nov 01 2009 16:39:19 GMT+0800 PLL Compensation warning Still not quite clear about this. Need to do a experiment myself.
Sun Nov 01 2009 16:37:35 GMT+0800 I need a low jitter clock mux in logic cells I have collected some Clock Mux Circuits too. Planning on a blog post about these tricky designs someday.
Sun Nov 01 2009 16:36:16 GMT+0800 Understanding Recovery and Removal in TimeQuest Will study it carefully when I have time.
Sun Nov 01 2009 16:35:14 GMT+0800 Ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks This one really helps. It guided my recent work to a success!

On the Boundaries:

Sun Nov 01 2009 17:08:20 GMT+0800 how to sample io pin using signaltap 2 logic analyzer? Need to do some experiments myself.
Sun Nov 01 2009 17:06:40 GMT+0800 lvds simulation of stratix 4 using cst design studio Can anyone help him/her/me?
Sun Nov 01 2009 17:04:11 GMT+0800 What kind of pad does the Quartus select when I configure the i/o as single-ended
Sun Nov 01 2009 17:01:12 GMT+0800 Differential pair and Single-ended pins in HSMC of StratixIII 3SL150 kit
Sun Nov 01 2009 16:55:36 GMT+0800 how to connect PLL output to default pin What we can do or what we cannot do with the PLLs/Clkctrls are never clear until we reached the P&R stage. Isn't this inconvenient?

Call me a "Flow Guy":

Sun Nov 01 2009 17:15:04 GMT+0800 How to maximize license utilization? Help myself!
Sun Nov 01 2009 17:03:16 GMT+0800 log files generated by Quartus. Can anyone help him/her/me?
Sun Nov 01 2009 16:50:47 GMT+0800 Handling Quartus executable return codes I've long been planning on a blog post about how to control the compilation flow within Tcl.

Tricks:

Sun Nov 01 2009 17:21:42 GMT+0800 How to extract 1bit from a bus in a Block Diagram/Schematic File
Sun Nov 01 2009 17:12:13 GMT+0800 X_on_violation_option