SystemVerilog -- 3.2 SystemVerilog foreach loop

SystemVerilog foreach loop

SystemVerilog数组是允许在单个变量中存储多个值的数据结构。循环仅用于遍历此类数组，并且是执行此操作的最简单和最简单的方法。foreach

Syntax

循环从0开始循环访问每个索引。如果循环中有多个语句，则必须像所有其他过程块一样用foreach和foreach begin end关键字括起来。

foreach (<variable>[<iterator>])
  // Single statemnet

foreach (<variable>[<iterator>]) begin
  // Multiple statemnets
end

Example #1: Single dimensional Arrays

module tb;
  int array[5] = '{1, 2, 3, 4, 5};
  int sum;

  initial begin
    foreach (array[i])
      $display ("array[%0d] = %0d", i, array[i]);

    foreach (array[l_index]) begin
      sum += array[l_index];
      $display ("array[%0d] = %0d, sum = %0d", l_index, array[l_index], sum);
    end
  end
endmodule

模拟日志

ncsim> run
array[0] = 1
array[0] = 2
array[0] = 3
array[0] = 4
array[0] = 5
array[0] = 1, sum = 1
array[0] = 2, sum = 3
array[0] = 3, sum = 6
array[0] = 4, sum = 10
array[0] = 5, sum = 15
ncsim: *W,RNQUIE: Simulation is complete.

Note that is just a shorter version to the following loop : `foreach` `for`

for (int i = 0; i < $size(array); i++) begin
  // Statements inside the for loop
end

Example #2: Multidimensional Arrays

module tb;
  int  md_array [5][2] = '{'{1,2}, '{3,4}, '{5,6}, '{7,8}, '{9,10}};

  initial begin
    foreach (md_array[i])
      foreach (md_array[i][j])
        $display ("md_array[%0d][%0d] = %0d", i, j, md_array[i][j]);
  end
endmodule

模拟日志

ncsim> run
md_array[0][0] = 1
md_array[0][1] = 2
md_array[1][0] = 3
md_array[1][1] = 4
md_array[2][0] = 5
md_array[2][1] = 6
md_array[3][0] = 7
md_array[3][1] = 8
md_array[4][0] = 9
md_array[4][1] = 10
ncsim: *W,RNQUIE: Simulation is complete.