SystemVerilog -- 3.0 SystemVerilog Loops
SystemVerilog Loops
What are loops ?
loop是一段不断执行的代码。条件语句通常包含在循环中，以便在条件变为真时终止。如果loop永远运行，那么模拟将无限期挂起。
下表给出了 SystemVerilog 中不同类型的循环构造。
| \ | \ |
|---|---|
| forever | Runs the given set of statements forever |
| repeat | Repeats the given set of statements for a given number of times |
| while | Repeats the given set of statements as long as given condition is true |
| for | Similar to while loop, but more condense and popular form |
| do while | Repeats the given set of statements atleast once, and then loops as long as condition is true |
| foreach | Used mainly to iterate through all elements in an array |
forever
这是一个无限循环。请注意，除非在模块中包含时间延迟以提前模拟时间，否则您的模拟将挂起。while (1) forever
module tb;
// This initial block has a forever loop which will "run forever"
// Hence this block will never finish in simulation
initial begin
forever begin
#5 $display ("Hello World !");
end
end
// Because the other initial block will run forever, our simulation will hang!
// To avoid that, we will explicity terminate simulation after 50ns using $finish
initial
#50 $finish;
endmodule
| 请注意，如果不调用模拟，模拟将无限期地继续进行。`$finish` |
模拟日志
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Simulation complete via $finish(1) at time 50 NS + 0
repeat
用于在块中重复语句一定次数。下面显示的示例将显示该消息5次，并继续执行其余代码。
module tb;
// This initial block will exexute a repeat statement that will run 5 times and exit
initial begin
// Repeat everything within begin and 5 times and exit "repeat" block
repeat (5) begin
$display ("Hello World !");
end
end
endmodule
模拟日志
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.
while
如果你知道verilog/C，你就已经知道了。只要条件为true，它就会重复该快。计数器最初为零，并递增直到达到10。
module tb;
bit clk;
always #10 clk = ~clk;
initial begin
bit [3:0] counter;
$display ("Counter = %0d", counter); // Counter = 0
while (counter < 10) begin
@(posedge clk);
counter++;
$display ("Counter = %0d", counter); // Counter increments
end
$display ("Counter = %0d", counter); // Counter = 10
$finish;
end
endmoudule
模拟日志
ncsim> run
Counter = 0
Counter = 1
Counter = 2
Counter = 3
Counter = 4
Counter = 5
Counter = 6
Counter = 7
Counter = 8
Counter = 9
Counter = 10
Counter = 10
Simulation complete via $finish(1) at time 190 NS + 0
for
与verilog/C类似，这允许您在同一行中提起起始值、条件和增量表达式。
module tb;
bit clk;
always #10 clk = ~clk;
initial begin
bit [3:0] counter;
$display ("Counter = %0d", counter); // Counter = 0
for (counter = 2; counter < 14; counter = counter + 2) begin
@(posedge clk);
$display ("Counter = %0d", counter); // Counter increments
end
$display ("Counter = %0d", counter); // Counter = 14
$finish;
end
endmodule
模拟日志
ncsim> run
Counter = 0
Counter = 2
Counter = 4
Counter = 6
Counter = 8
Counter = 10
Counter = 12
Counter = 14
Simulation complete via $finish(1) at time 110 NS + 0
do while
这将首先执行代码，然后检查条件以查看是否应再次执行代码。
module tb;
bit clk;
always #10 clk = ~clk;
initial begin
$display ("Counter = %0d", counter); // Counter = 0
do begin
@(posedge clk);
counter ++;
$display ("Counter = %0d", counter); // Counter increments
end while (counter < 5);
$display ("Counter = %0d", counter); // Counter = 14
$finish;
end
endmodule
模拟日志
ncsim> run
Counter = 0
Counter = 1
Counter = 2
Counter = 3
Counter = 4
Counter = 5
Counter = 5
Simulation complete via $finish(1) at time 90 NS + 0
foreach
这最适合循环数组变量，因为您不必找到数组大小，将变量设置为从0开始到array_size-1，并在每次迭代时递增它。
module tb_top;
bit [7:0] array [8]; // create a fixed size array
initial begin
// Assign a value to each loaction in the array
foreach (array[index]) begin
array[index] = index;
end
// Iterate through each location and print the value of current location
foreach (array[index]) begin
$display ("array[%0d] = 0x%0d", index, array[index]);
end
end
endmodule
模拟日志
ncsim> run
array[0] = 0x0
array[1] = 0x1
array[2] = 0x2
array[3] = 0x3
array[4] = 0x4
array[5] = 0x5
array[6] = 0x6
array[7] = 0x7
ncsim: *W,RNQUIE: Simulation is complete.
