SystemVerilog -- 2.12 Data Types ~ SystemVerilog Structure

SystemVerilog Structure

Structure可以包含不同数据类型的元素，这些元素可以作为一个整体引用，也可以通过其名称单独引用。这些元素具有相同数据类型的数组完全不同。

// Normal arrays -> a collection of variables of same data type
int array [10];          // all elements are of int type
bit [7:0] mem [256];     // all elements are of bit type

// Structures -> a collection of variables of different data types
struct {
  byte   val1;
  int    val2;
  string val3;
}; struct_name;

Syntax

struct {
  [list of variables]
} struct_name;

Unpacked Structures

默认情况下，结构是unpacked的，可以使用关键字进行定义，并且可以在大括号内提供成员声明列表，后跟structure的名称。struct

Structure Example

module tb;
  // Create a structure called "st_fruit"
  // which to store the fruit's name, count and expiry date in days.
  // Note : this structure declaration can also be placed outside the module
  struct {
    string fruit;
    int    count;
    byte   expiry;
  } st_fruit;

  initial begin
    // st_fruit is a structure variable, so let's initialize it
    st_fruit = '{"apple", 4, 15};
    
    // Display the structure variable
    $display ("st_fruit = %p", st_fruit);

    // Change fruit to pineapple, and expiry to 7
    st_fruit.fruit  = "pineapple";
    st_fruit.expiry = 7;
    $display ("st_fruit = %p", st_fruit);
  end
endmodule

模拟日志

ncsim> run
st_fruit = '{fruit:"apple", count:4, expiry:'hf}
st_fruit = '{fruit:"pineapple", count:4, expiry:'hf}
ncsim: *W,RNQUIE: Simulation is complete

What is the need to typedef a structure ?

在上面的示例中只创建了一个变量，但如果需要创建具有相同成分的多个structure变量，则最好通过创建structure的用户定义数据类型。然后st_fruit将成为一个数据类型，然后可用于创建该类型的变量。typedef

module tb;
  // Create a structure called "st_fruit"
  // which to store the fruit's name, count and expiry date in days
  // Note : this structure declaration can also be placed outside the module
  typedef struct {
    string fruit;
    int    count;
    byte   expiry;
  } st_fruit;

  initial begin
    // st_fruit is a data tyoe, so we need to declare a varible of this data type
    st_fruit fruit1 = '{"apple", 4, 15};
    st_fruit fruit2;

    // Display the structure variable
    $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);

    // Assign one structure variable to another and print 
    // Note that contents of this variable is copied into the other
    fruit2 = fruit1;
    $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);
    
    // Change fruit1 to see if fruit2 is affected
    fruit1.fruit = "orange";
    $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);
  end
endmodule

模拟日志

ncsim> run
fruit1 = '{fruit:"apple", count:4, expiry:'hf}   fruit2 = '{fruit:"", count:0, expiry:'h0}   
fruit1 = '{fruit:"apple", count:4, expiry:'hf}   fruit2 = '{fruit:"apple", count:4, expiry:'hf} 
fruit1 = '{fruit:"orange", count:4, expiry:'hf}   fruit2 = '{fruit:"apple", count:4, expiry:'hf} 
ncsim: *W,RNQUIE: Simulation is complete

Packed Structures

Packed Structures是一种将向量细分为字段的机制，这些字段可以作为成员访问，并在内存中打包在一起，没有间隙。Structure中的第一个成员是最重要的，随后的成员按重要性递减的顺序排列。

使用关键字声明Packed Structure，默认情况下该关键字是无符号的。packed

Example

// Create a "packed" structure data type which is similar to creating
// bit [7:0] ctrl_reg
// ctrl_reg [0]   represents en
// ctrl_reg [3:1] represents cfg
// ctrl_reg [7:4] represents mode
typedef struct packed {
  bit [3:0] mode;
  bit [2:0] cfg;
  bit       en;
} st_ctr1;

module tb;
  st_ctr1   ctrl_reg;

  initial begin
    // Initialize paacked structure variable
    ctrl_reg = '{4'ha, 3'h5, 1};

    // Change packed structure member to something else
    ctrl_reg.mode = 4'h3
    $display ("ctrl_reg = %p", ctrl_reg);

    // Assign a packed value to the structure variable
    ctrl_reg = 8'hfa;
    $display ("ctrl_reg = %p", ctrl_reg);
  end
endmodule

模拟日志

ncsim> run
ctrl_reg = '{mode:'ha, cfg:'h5, en:'h1}
ctrl_reg = '{mode:'h3, cfg:'h5, en:'h1}
ctrl_reg = '{mode:'hf, cfg:'h5, en:'h0}
ncsim: *W,RNQUIE: Simulation is complete