SystemVerilog -- 2.7 Data Types ~ SystemVerilog Unpacked Arrays

SystemVerilog Unpacked Arrays

Unpacked Arrays用于引用在变量名称之后声明的维度。

Unpacked Arrays可以是固定大小的数组、动态数组、关联数组、队列。

Single Dimensional Unpacked Array

module tb;
  byte    stack [8];      // depth = 8, 1 byte wide variable
  initial begin
    // Assign random values to each slot of the stack
    foreach (stack[i]) begin
      stack[i] = $random;
      $display ("Assign 0x%0h to index %0d", stack[i], i);
    end
    // Print contents of the stack
    $display ("stack = %p", stack);
  end
endmodule

模拟日志

Assign 0x24 to index 0
Assign 0x81 to index 1
Assign 0x9  to index 2
Assign 0x63 to index 3
Assign 0xd  to index 4
Assign 0x8d to index 5
Assign 0x65 to index 6
Assign 0x12 to index 7
stack = '{'h24, 'h81, 'h9, 'h63, 'hd, 'h8d, 'h65, 'h12}

Multidimensional Unpacked Array

module tb;
  byte stack [2][4];   // 2 rows, 4 cols
  initial begin
    // Assign random values to each slot of the stack
    foreach (stack[i]) begin
      foreach (stack[i][j]) begin
        stack[i][j] = $random;
        $display ("stack[%0d][%0d] = 0x%0h", i, j, stack[i][j]);
      end
    end
    // Print contents of the stack
    $display ("stack = %p", stack);
  end
endmodule

模拟日志

ncsim> run
stack[0][0] = 0x24
stack[0][1] = 0x81
stack[0][2] = 0x9
stack[0][3] = 0x63
stack[1][0] = 0xd
stack[1][1] = 0x8d
stack[1][2] = 0x65
stack[1][3] = 0x12
stack = '{' {'h24, 'h81, 'h9, 'h63}, '{'hd, 'h8d, 'h65, 'h12}}
ncsim: *W,RNQUIE: Simulation is complete.

Packed + Unpacked Array

下面显示的示例演示了一个多维packed+unpacked数组。

module tb;
  bit [3:0][7:0]  stack [2][4];   // 2 rows, 4 cols
  initial begin
      // Assign random values to each slot of the stack
      foreach (stack[i]) begin
        foreach (stack[i][j]) begin
          stack[i][j] = $random;
          $display ("stack[%0d][%0d] = 0x%0h", i, j, stack[i][j]);
        end
      end
      
      // Print contents of the stack
      $display ("stack = %p", stack);
      // Print content of a given index
      $display ("stack[0][0][2] = 0x%0h", stack[0][0][2]);
  end
endmodule

模拟日志

ncsim> run
stack[0][0] = 0x12153524
stack[0][1] =
stack[0][2] =
stack[0][3] =
stack[1][0] =
stack[1][1] =
stack[1][2] =
stack[1][3] =
stack = ' {' {'h12153524, 'hc0895e81, 'h8484d609, 'hb1f05663}, '{'h6b97b0d, 'h46df998d, 'hb2c28465, 'h89375212}}
ncsim: *W,RNQUIE: Simulation is complete.

在多维声明中，名称前声明的维度比名称后方的维度变化更快。

bit [1:4]      m_var  [1:5]        // 1:4 varies faster than 1:5
bit            m_var2 [1:5][1:3]   // 1:3 varies faster than 1:5
bit [1:3][1:7] m_var3              // 1:7 varies faster than 1:3
bit [1:3][1:2] m_var4 [1:7][0:2]   // 1:2 varies most rapidly, followed by 1:3, then 0:2 and then 1:7