摘要:
今天做了几个Xilinx大学计划里的Spartan-3E Starter的例子,在Lab4中有个很有趣的Synthesize Report:Minimum period (Verilog): ~12 ns (Maximum Frequency: ~83 MHz)Minimum period (VHDL): ~10.5 ns (Maximum Frequency: ~95 MHz) Slices 167 (Verilog)/ 163 (VHDL) Slice Flip Flops 148 (Verilog)/ 147 (VHDL) 4 input LUTs 303 (Verilog)/ 298 阅读全文