Duplicated to reduce fanout and improve timings

FPGA:  Duplicated to reduce fanout and improve timings

example:

signal address_0 : std_logic_vector(11 downto 0);
signal address_1 : std_logic_vector(11 downto 0);
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of address_0: signal is "NO";
attribute equivalent_register_removal of address_1: signal is "NO"; 

process(clk)
begin
if clk'event and clk='1' then
-- Duplicated to reduce fanout and improve timings.
address_0 <= datain(27 downto 16);
address_1 <= datain(27 downto 16);
end if;
end process;

Only use address_0 in another process.

 

Xilinx FPGA link: http://www.xilinx.com/support/answers/40090.htm

Attribute previous related link:http://www.cnblogs.com/sundance/archive/2012/11/02/2751018.html

 

Made by Tim.