VHDL中attribute keep of xxx: signal is "true";的用法

attribute keep of error_channelb: signal is "true"; 

用法就是 keep a signal after mapping; 如果要用chipscope和在ucf文件中直接使用信号名的,可用keep这保持,这样可方便我们添加观察信号和添加约束.

 

Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file – Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. To ensure that a particular signal name ends up in the NCD, it’s important to use the “keep” signal constraint.

When a design is mapped, some nets may be absorbed into logic blocks. The mapping tool does this because as a signal passes from one logic block to another, it can change name in your HDL code (eg. from data_in to data_out). As it is the same signal, the mapping tool gives it ONE name and it chooses among the names you have given it in your code.

When a net is absorbed into a block, it can no longer be seen in the physical design database. What this means in a practical sense is that you will no longer be able to refer to it in your UCF, and you will not find it in Chipscope inserter.

The “keep” constraint is a constraint that you put in your HDL code that prevents the signals you specify from being absorbed away.

In VHDL, before the “begin” statement, you must define “keep” as a string attribute and then assign the keep attributes as “true” for all the signals you want to keep.

attribute keep : string;
attribute keep of MyRefClk : signal is "true";
attribute keep of MyData   : signal is "true";

 

In Verilog, you would use the following lines:

// synthesis attribute keep [of] MyRefClk [is] "true";
// synthesis attribute keep [of] MyData [is] "true";

 

Both examples will keep the signal names “MyRefClk” and “MyData” in the physical design database and you will be able to refer to them in your UCF file and find them in Chipscope inserter.

 

Examples:

signal channela_plus_one : std_logic_vector(13 downto 0);
attribute keep of channela_plus_one: signal is "true";
signal channelb_plus_one : std_logic_vector(13 downto 0);
attribute keep of channelb_plus_one: signal is "true";  
signal error_channela : std_logic;
attribute keep of error_channela: signal is "true";
signal error_channelb : std_logic;
attribute keep of error_channelb: signal is "true";

 

Related Link:http://www.fpgadeveloper.com/2011/06/how-to-keep-a-signal-name-after-mapping.html

Xilinx link : http://forums.xilinx.com/t5/Synthesis/How-to-avoid-signal-optimizing-in-synthesis/td-p/76056

Made by Tim.