随笔-处理器微架构-Types of Cache Misses

There are several types of cache misses, broadly categorized into compulsory, capacity, and conflict misses. These three are often referred to as the "3Cs" 1. A fourth type, coherence misses, arises in multi-processor systems 1.

• Compulsory misses, also known as cold misses or first-reference misses, occur when a data block is accessed for the first time and is not yet present in the cache 12345. These are unavoidable unless the data is prefetched 1.

• Capacity misses happen when the cache is too small to hold all the data needed by a program, resulting in previously cached data being evicted to make room for new data 1245. These are essentially non-compulsory misses in a fully associative cache 1.

• Conflict misses, also called collision or interference misses, occur due to the cache's mapping scheme. Data may be present in the cache, but it's located in a cache line that's already occupied by another data block that maps to the same location 124.

• Coherence misses are specific to multi-processor systems. They occur when a cache line is invalidated by a write operation from another processor, causing a subsequent access to miss 12. This is related to maintaining cache coherence across multiple processors.

参考：

• https://redis.io/glossary/cache-miss/