[笔记]VGA建模之一(Display a rectangle)
一、RTL视图:
二、
sync_module
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 | module sync_module( input VGA_CLK, //800x600 input RST_N, output VGA_HS,VGA_VS,valid, output[10:0] X,Y //column and row addr signal ); reg[10:0] Count_H; always@(posedge VGA_CLK or negedge RST_N) if (!RST_N) Count_H<=11'd0; else if (Count_H==11'd1056) Count_H<=11'd0; else Count_H<=Count_H+1'b1; reg[10:0] Count_V; always@(posedge VGA_CLK or negedge RST_N) if (!RST_N) Count_V<=11'd0; else if (Count_V==11'd628) Count_V<=11'd0; else if (Count_H==11'd1056) Count_V<=Count_V+1'b1; reg valid_r; always@(posedge VGA_CLK or negedge RST_N) if (!RST_N) valid_r<=1'b0; else if ((Count_H>216&&Count_H<1017)&&(Count_V>11 'd27&&Count_V<11' d627)) valid_r<=1'b1; else valid_r<=1'b0; assign VGA_HS=(Count_H<=11 'd128) ? 1' b0 : 1'b1; assign VGA_VS=(Count_V<=11 'd4) ? 1' b0 : 1'b1; assign valid=valid_r; assign X=valid_r ? Count_H-11 'd217 : 11' d0; assign Y=valid_r ? Count_V-11 'd28 : 11' d0; endmodule |
vga_control_module
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | module vga_control_module( input VGA_CLK, input RST_N, input[10:0] X,Y, input valid, output[7:0] VGA_R,VGA_G,VGA_B ); reg rectangle; always@(posedge VGA_CLK or negedge RST_N) if (!RST_N) rectangle<=1'b0; //else if(X>11'd0&&Y<11'd100) else if ((X>11 'd0&&X<11' d100)||(X>11 'd700&&X<11' d800)||(Y>11 'd0&&Y<11' d100)||(Y>11 'd500&&Y<11' d600)) rectangle<=1'b1; else rectangle<=1'b0; assign VGA_R=valid&&rectangle ? 8 'b1111_1111 : 8' b0; assign VGA_G=valid&&rectangle ? 8 'b1111_1111 : 8' b0; assign VGA_B=valid&&rectangle ? 8 'b1111_1111 : 8' b0; endmodule |
vga_module
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 | //* Display a rectangle module vga_module( input CLOCK_50, input[3:0] KEY, output VGA_CLK, output[7:0] VGA_R,VGA_G,VGA_B, output VGA_HS,VGA_VS, output VGA_BLANK_N, output VGA_SYNC_N ); assign VGA_SYNC_N=1'b0; //If not SOG,Sync input should be tied to 0; assign VGA_BLANK_N=VGA_HS&&VGA_VS; pll_module u1( .inclk0 ( CLOCK_50 ), .c0 ( VGA_CLK ) //VGA_CLK=CLK_40=1056x628x60; ); wire[10:0] X,Y; wire valid; wire RST_N; assign RST_N=KEY[0]; sync_module u2( .VGA_CLK(VGA_CLK), .RST_N(RST_N), .VGA_HS(VGA_HS), .VGA_VS(VGA_VS), .X(X), .Y(Y), .valid(valid) ); vga_control_module u3( .VGA_CLK(VGA_CLK), .RST_N(RST_N), .VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B), .X(X), .Y(Y), .valid(valid) ); endmodule |
posted on 2011-08-16 20:34 LiangXuan 阅读(3325) 评论(4) 编辑 收藏 举报
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