[Xilinx]产生任意Duty的PWM波形仿真
pwm.v
1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: LiuQiang 5 // 6 // Create Date: 19:32:34 05/13/2013 7 // Design Name: 8 // Module Name: pwm 9 // Project Name: 10 // Target Devices: 11 // Tool versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 module pwm( 22 input clk_50, 23 input rst_n, 24 output reg clk_1m, //1MHz clock 25 output reg pwm_wave 26 ); 27 //parameter X = 40; 28 //parameter duty = X/100; 29 reg rst_n1,rst_n2; 30 31 32 parameter PERIOD = 50, 33 PULSEWIDTH = 25, 34 SIZE =16; //50=110010,共6位 35 reg[SIZE-1:0] counter_div; 36 37 38 parameter DUTY = 40; //40% 39 40 reg [6:0] pwm_counter; 41 42 //reg X; 43 //reg duty; 44 ////////////////////////////////////////////////////////////////////////////////// 45 //异步复位，同步释放 46 always@(posedge clk_50 or negedge rst_n) 47 if(!rst_n) 48 rst_n1<=0'b0; 49 else 50 rst_n1<=1'b1; 51 52 always@(posedge clk_50 or negedge rst_n) 53 if(!rst_n) 54 rst_n2<=1'b0; 55 else 56 rst_n2<=rst_n1; 57 ////////////////////////////////////////////////////////////////////////////////// 58 //generator 1MHz clock; 59 always@(posedge clk_50 or negedge rst_n2) 60 if(!rst_n2) 61 counter_div<=0; 62 else if(counter_div<PERIOD-1) 63 counter_div<=counter_div+1'b1; 64 else 65 counter_div<=1'b0; 66 67 always@(posedge clk_50 or negedge rst_n2) 68 if(!rst_n2) 69 clk_1m<=0; 70 else if(counter_div<PULSEWIDTH) 71 clk_1m<=1; 72 else 73 clk_1m<=0; 74 //Modelsim verify ok! 75 ////////////////////////////////////////////////////////////////////////////////// 76 77 always@(posedge clk_1m or negedge rst_n2) 78 begin 79 if(!rst_n2) 80 pwm_counter<=1'b0; 81 else if(pwm_counter==99) 82 pwm_counter<=1'b0; 83 else 84 pwm_counter<=pwm_counter+1'b1; 85 end 86 87 always@(posedge clk_1m or negedge rst_n2) 88 begin 89 if(!rst_n2) 90 pwm_wave <= 1'b0; 91 else if(pwm_counter==0) 92 pwm_wave <= 1'b1; 93 else if(pwm_counter<DUTY) 94 pwm_wave <= 1'b1; 95 else 96 pwm_wave <= 1'b0; 97 end 98 //Modelsim verify ok! 99 endmodule
pwm_tb.v
1 `timescale 1ns / 1ns 2 3 //////////////////////////////////////////////////////////////////////////////// 4 // Company: 5 // Engineer: 6 // 7 // Create Date: 20:00:37 05/07/2013 8 // Design Name: pwm 9 // Module Name: F:/XilinxStudy/XilinxApp/pwm/pwm_tb.v 10 // Project Name: pwm 11 // Target Device: 12 // Tool versions: 13 // Description: 14 // 15 // Verilog Test Fixture created by ISE for module: pwm 16 // 17 // Dependencies: 18 // 19 // Revision: 20 // Revision 0.01 - File Created 21 // Additional Comments: 22 // 23 //////////////////////////////////////////////////////////////////////////////// 24 25 module pwm_tb; 26 27 // Inputs 28 reg clk_50; 29 reg rst_n; 30 31 // Outputs 32 wire pwm_wave; 33 34 // Instantiate the Unit Under Test (UUT) 35 pwm pwm_tb ( 36 .clk_50(clk_50), 37 .rst_n(rst_n), 38 .clk_1m(clk_1m), 39 .pwm_wave(pwm_wave) 40 ); 41 42 parameter PERIOD = 20; 43 initial begin 44 // Initialize Inputs 45 clk_50 = 0; 46 forever 47 #(PERIOD/2) clk_50=~clk_50; 48 end 49 50 initial begin 51 rst_n = 0; 52 #100 rst_n=1; 53 end 54 endmodule
wave
