【原创】DC的一些命令

 

0 clock 命令：Tcl Built-In Commands

clock seconds：

Return the current date and time as a system-dependent

integer value. The unit of the value is seconds, allowing it to be used for relative time calculations.

 

1. file 命令：Tcl Built-In Commands

   file option name ?arg arg ...?

file exists name：

Returns 1 if file name exists and the current user has

search privileges for the directories leading to it, 0 otherwise.

 

1. exec函数族的作用是根据指定的文件名找到可执行文件，并用它来取代调用进程的内容，换句话说，就是在调用进程内部执行一个可执行文件。

   mkdir 目录名：创建目录

 

1. define_design_lib命令：

结构：define_design_lib library_name -path directory

The define_design_lib command maps a design library to a UNIX direc-tory. The directory is used to store intermediate representations of designs.

 

1. sh 是 shell 的简称，在执行脚本的时候是用sh + 脚本名的方式来执行；

   sh rm -rf ./output/* 其中，rm 是文件目录删除命令，-f 直接删除，-r 全部删除 ，*匹配任意长的字符。

 

1. alib_library_analysis_path：

   Specifies a single path, similar to a search path, for reading and writing the alib files that correspond to the target libraries.This variable specifies the path from which the tool loads alibs during compile

    

2. source命令: Read a file and evaluate it as a Tcl script.

   结构：source [-echo] [-verbose] [-continue_on_error] file

   -echo Echoes each command as it is executed. Note that this option is

   a non-standard extension to Tcl.

   -verbose

   Displays the result of each command executed. Note that error

   messages are displayed regardless. Also note that this option

   is a non-standard extension to Tcl.

 

1. Default: target_library = "your_library.db"

   link_library = "* your_library.db"

   target_library: Specifies the list of technology libraries of components to be used when compiling a design.

   link_library : Specifies the list of design files and libraries used during linking.

2. suppress_message命令：suppress_message [message_list]

   Disables printing of one or more informational or warning messages.

 

1. suppress_errors命令：

   Specifies a list of error codes for which messages are to be suppressed during the current shell session.

 

1. symbol_library：Specifies the symbol libraries to use during schematic generation

 

1. verbose_messages ：Causes more explicit system messages to be displayed during the current session.

    

2. auto_link_options :This variable specifies the link command options to be used when link is invoked automatically. The default value is -all.

    

3. verilogout_no_tri : Declares three-state nets as Verilog "wire" instead of "tri." This variable is useful in eliminating "assign" primitives and "tran" gates in the Verilog output.

    

4. dc_shell_status :Contains the return value of the previously executed command.Therefore the variable can be of anytype.Most commands return the integer 0 to indicate failure or 1 to indicate successful execution. This variable is most often used as the conditional expression of an if or while command.

    

5. sh_new_variable_message :The sh_new_variable_message variable controls a debugging feature for tracing the creation of new variables.Its primary debugging purpose is to catch the misspelling of an application-owned global variable. When set to true, an informational message (CMD-041) is displayed when a variable is defined for the first time at the command line. When set to false, no message is displayed.

    

6. compile_seqmap_propagate_constants : Controls whether the compile command tries toi dentify and remove constant registers and propagate the constant value throughout the design. When the value is true (the default), compile tries to identify and remove constant sequential elements in the design, which improves the area of the design.

    

7. compile_delete_unloaded_sequential_cells :

   Controls whether the compile command deletes unloaded sequential cells. By default, the compile command deletes unloaded sequential cells. To retain such cells, set the compile_delete_unloaded_sequential_cells variable to false.

    

8. compile_preserve_subdesign_interfaces :

   Controls whether the compile command preserves the subdesign interface. When this variable is set to true, it disables customization of logic external to a subdesign during compile, and preserves the subdesign interface. When set to false (the default), compile customizes the logic external to a subdesign based on the subdesign's internal logic.

 

1. hdlin_preserve_sequential :

   Controls whetherthe elaborate and read commands retain unloaded sequential cells in the design.

 

1. hdlin_enable_rtldrc_info :

   When true, RTL TestDRC filename and linenumber information is created for designs processed by subsequent dc_shell commands.When false, no RTL TestDRC information is created.

 

1. echo 命令：显示输出

 

1. dont_use命令：

Disables the specified library cells so that they are not added to a design during compile. Set with set_dont_use.

 

1. alias 命令：为一个可执行程序定义别名

 

1. "dc_shell -f tcl/dc.tcl | tee dc.log"

   dc_shell -f 文件名 表明启动dc_shell后自动执行可执行文件；

   "|"是管道机制符号，命令1 |命令2|…|命令n 管道机制是前一个命令的输出作为后一个命令的输入；

   tee命令：tee [-ai] filename 读取标准输入的数据，并将其内容输出到指定文件，默认为覆盖方式，-a 表示追加方式

 

1. report_timing 命令：Displays timing information about a design。

   report_timing [options] :

   [options]举例如下：

   [-sig 数字] =>[ -significant_digits digits] Specifies the number of digits to the right of the decimal point to report. Allowed values are from 0 through 13. The default is 2.

[-cap] =>[-capacitance] Indicates that total (lump) capacitance be shown in the path report.

[-tran]=>[-transition_time] Shows the net transition time for each driving pin in the path report.

[-nets] Shows nets in the path report.The default is not to show nets.To show the delay for the nets, use the -input_pins option.

[-input_pins] Shows input pins in the path report. The default is to show only output pins. This option also shows the delays of the nets connected to these pins.

[-to to_list]Reports only the paths to the named pins, ports, or clocks.

[-from from_list] Reports only the paths from the named pins, ports, or clocks

 

1. set_svf 命令：set_svf filename [-append][-off]

   Generates a Formality setup information file for efficient compare point matching in Formality

   This command causes Design Compiler to start recording setup information for Formality, the Synopsys formal verification tool. The SVF ("Setup Verification for Formality") file that is produced is used by Formality during the matching step to facilitate the alignment of compare points.

 

1. analyze 命令： analyze [options] file_list

   Analyzes the specified HDL source files; stores the design templates they define into the specified library in a format ready to elaborate and specialize as needed to link a full design.

Some options:

[-format verilog | sverilog | vhdl] : Specifies the format of the files that are to be analyzed. The supported formats are Verilog, SystemVerilog, and VHDL.

 

1. elaborate 命令：elaborate design_name [options]

   Builds a design from the intermediate format of a Verilog module, a VHDL entity and architecture, or a VHDL configuration.

   -Reads the intermediate files；-builds the 'GTECH' design in DC memory (unmapped ddc format)；-Sets the current design to the specified design；- Links and auto-loads the specified design；

   - Allows specification of parameter values:

 

1. current_design命令（before link）: sets the working design

   current_design [design] The current_design command sets the working design for many commands. If you do not specify any arguments, the current_design command returns the name of the current working design.

 

30 link 命令：Resolves design references. 语法结构：link ，没有参数；

Performs a name-based resolution of design references for the current design.

For a design to be complete, it needs to be connected to all of the library components and designs it references. The references must be located and linked to the current design in order for the design to be functional. The purpose of this command is to locate all of the designs and library components referenced in the current design and connect (link) them to the current design.

 

31 uniquify_naming_style ：Specifies the naming convention to be used by the uniquify command. The variable string must contain only one %s (percent s) and one %d (percent d) character sequence. To use a percent sign in the design name, two are needed in the string (%%).

 

32 uniquify命令：uniquify [-force]|[other options]

Removes multiply-instantiated hierarchy in the current design by creating a unique design for each cell instance.If a new design is generated, it is copied from the original design, and placed in the same file as the current design. The new design is named according to the uniquify_naming_style variable.

[-force] Indicates that instances are to be renamed even if they are already unique or are assigned the dont_touch attribute. The top-level design is not renamed.

 

33 write 是write_file 的别名 ：Writes a design netlist or schematic from memory to a file.

结构：write_file [-format output_format] [-hierarchy] [-no_implicit] [-output output_file_name][-scenarios scenario_list][-library library_name] [-include_anchor_cells] [design_list]

[-format output_format]: Specifies the output format of the design. the default format is ddc;other format ：verilog，svsim, vhdl

[-hierarchy]: Writes out all the designs in the hierarchy, starting from the designs specified in design_list.

[-output output_file_name]:Specifies a single file into which designs are to be written.By default,the command writes each design into a separate file named design.suffix, .ddc –ddc;.v –verilog ; .sv –svsim;.vhd -vhdl

 

34 remove_sdc命令：Removes all Synopsys Design Constraints (SDC).

 

35 remove_clock 命令：remove_clock clock_list | -all

Removes clocks from the current design

 

36 reset_design命令，没有参数：Removes all user-specified objects and attributes from the current design, except those defined by using the set_attribute command.

 

37 create_clock命令：Creates a clock object and defines its waveform in the current design.

语法：create_clock [-name clock_name] [-add] [source_objects] [-period period_value] [-waveform edge_list] [-comment comment_string]

[-name clock_name] ：Specifies the name of the clock being created.

[-period period_value]: Specifies the period of the clock waveform in library time units

[-waveform edge_list]: Specifies the rise and fall edge times, in library time units, of the clock over an entire clock period.

[source_objects]: Specifies a list of pins or ports on which to apply this clock.

 

38 get_pins命令：Creates a collection of pins that match the specified criteria。

get_ports 命令：Creates a collection of ports from the current design that match the specified criteria.

all_inputs 命令：Returns a collection of input or inout ports in the current design.

all_outputs命令：Returns a collection of output or inout ports in the current design.

 

39 get_clocks命令：Creates a collection of clocks from the current design.

get_designs ：Creates a collection of one or more designs loaded into the tool.

get_nets : Creates a collection of nets that match the specified criteria.

 

40 set_clock_latency命令：Specifies clock network latency.

set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-early] [-late] [-clock clock_list] delay object_list

[delay]: Specifies the clock latency value.

[object_list] :Specifies the clocks, ports, and pins for which the clock latency is to be set.

 

41 set_clock_uncertainty命令：Specifies the uncertainty (skew) of the specified clock networks.

set_clock_uncertainty [object_list | -from from_clock | -rise_from rise_from_clock | -fall_from fall_from_clock -to to_clock | -rise_to rise_to_clock | -fall_to fall_to_clock] [-rise] [-fall] [-setup] [-hold] uncertainty

[-setup ]:Indicates that the uncertainty applies only to setup checks. By default, the uncertainty applies to both setup and hold checks.

 

42 set_input_delay命令：Sets input delay on pins or input ports relative to a clock signal.

set_input_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-clock_fall] [-level_sensitive] [-network_latency_included] [-source_latency_included] [-rise] [-fall] [-max] [-min] [-add_delay] port_pin_list

 

43 remove_from_collection命令：Removes objects from a collection, resulting in a new collection. The base collection remains unchanged.

 

44 set_output_delay 命令：Sets output delay on pins or output ports relative to a clock signal。

set_output_delay delay_value [-reference_pin pin_port_name] [-clock clock_name [-clock_fall] [-level_sensitive]] [-network_latency_included] [-source_latency_included] [-rise] [-fall] [-max] [-min] [-add_delay] [-group_path group_name] port_pin_list

 

45 set_input_transition命令：Sets the max_transition_rise, max_transition_fall, min_transition_rise, or min_transition_fall attributes to the specified transition values on the specified input and inout ports.

set_input_transition transition [-rise] [-fall][-min][-max] port_list

 

46 set_driving_cell命令：Sets attributes on input or inout ports of the current design that specify that a library cell or output pin of a library cell drives the specified ports.

set_driving_cell [-lib_cell lib_cell_name] [-library lib] [-rise] [-fall] [-min] [-max] [-pin pin_name] [-from_pin from_pin_name] [-dont_scale] [-no_design_rule] [-none] [-input_transition_rise rtran] [-input_transition_fall ftran] [-multiply_by factor] port_list [-cell obsolete_-_please_use_-lib_cell_instead]

 

47 set_load命令：Sets the load attribute on the specified ports and nets.

set_load value objects [-subtract_pin_load] [-min] [-max] [[-pin_load] [-wire_load]]

 

48 set_multicycle_path命令：Modifies the single-cycle timing relationship of a constrained path.

set_multicycle_path path_multiplier [-rise |-fall] [-setup |-hold] [-start |-end] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise_through rise_through_list] [-fall_through fall_through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-reset_path] [-comment comment_string]

 

49 set_max_delay命令：Specifies a maximum delay target for paths in the current design.

 

50 auto_wire_load_selection : Controls automatic selection of wire load model.

 

51 set_wire_load_mode : set_wire_load_mode mode_name

Sets the wire_load_model_mode attribute on the current design, specifying how wire load models are to be used to calculate wire capacitance in nets.

 

52 set_wire_load_model :

set_wire_load_model -name model_name [-library lib] [-min] [-max] [object_list]

Sets the wire_load_attach_name attribute on designs, ports, hierarchical cells of current design, for selecting a wire load model to use in calculating wire capacitance.

 

53 remove_propagated_clock : This command removes the propagated clock specification from clocks, ports, or pins in the current scenario.

 

54 set_max_transition: set_max_transition transition_value [-data_path] [-clock_path] object_list

Sets the maximum transition time for the specified clocks, ports, or designs.

 

55 set_max_capacitance: set_max_capacitance capacitance_value [-data_path] [-clock_path] object_list

Sets the max_capacitance attribute to a specified value on the specified clocks, ports and n designs.

 

56 set_max_fanout : set_max_fanout fanout_value object_list

Sets the max_fanout attribute to a specified value on specified input ports and designs.

 

57 set_critical_range : set_critical_range range_value designs

Sets the critical_range attribute to a specified value on a list of designs.

 

58 set_max_area : This commandsetsthe max_area attribute to area on thecurrentdesign.The max_area attribute represents the target area of the design and is used by the compile command to calculate area cost of the design.

 

59 set_dont_touch命令：set_dont_touch object_list [true |false]

Sets the dont_touch attribute oncells,nets,references,anddesignsinthecurrent design, and on library cells, to prevent modification or replacement of these objects during optimization.

 

60 set_dont_touch_network

Sets the dont_touch_network attribute on clocks, pins, or ports in the current design to prevent cells and nets in the transitive fanout of the set_dont_touch_network objects from being modified or replaced during optimization.

 

61 set_ideal_network : Marks a set of ports or pins in the current design as sources of an ideal network. This disables timing update and optimization of cells and nets in the transitive fanout of the specified objects.

 

62 filter_collection : Filters an existing collection, resulting in a new collection. The base collection remains unchanged.

 

63 get_attribute : Returns the value of an attribute on a list of design or library objects

 

64 group_path命令：Groups a set of paths for cost function calculations.

group_path [-weight weight_value] [-critical_range range_value] -default |-name group_name [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list | -rise_through rise_through_list | -fall_through fall_through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-comment comment_string]

Groups enable you to specify a set of paths to optimize even though there might be larger violations in another group.

 

65 check_timing ： Checks for possible timing problems in the current design.

check_design ： Checks the current design for consistency.

 

66 set_host_options 命令：set_host_options -max_cores number_of_cores

Controls the maximum number of CPU cores that can be used for parallel execution.

 

67 set_fix_multiple_port_nets ：

set_fix_multiple_port_nets -default |-all [-feedthroughs] [-outputs] [-constants] [-buffer_constants] [design_list]

Sets the fix_multiple_port_nets attribute to a specified value on the current design or a list of designs. This attribute controls whether compile inserts extra logic into the design to ensure that there are no feedthroughs, or that there are no two output ports connected to the same net at any level of hierarchy.

 

68 compile_ultra 命令：Performs a high-effort compile on the current design for better quality of results (QoR). compile=>Performs logic-level and gate-level synthesis and optimization on the current design.

compile_ultra [-incremental] [-scan] [-exact_map] [-no_autoungroup] [-no_seq_output_inversion] [-no_boundary_optimization] [-no_design_rule |-only_design_rule] [-timing_high_effort_script | -area_high_effort_script] [-top] [-retime] [-gate_clock] [-self_gating] [-check_only] [-congestion] [-spg]

[-no_autoungroup]: Specifies that automatic ungrouping is completely disabled. All hierarchies are preserved unless otherwise specified.

[-incremental ] :Runs compile_ultra in incremental mode. In the incremental mode, the tool does not run the mapping or implementation selection stages.

[-scan]: Enables the examination of the impact of scan insertion on mission-mode constraints during optimization, as in a normal compile. Use this option to replace all sequential elements during optimization.

[-no_boundary_optimization]:Specifies that no hierarchical boundary optimization is to be performed. By default, boundary optimization is turned on during compile_ultra activity.

[-no_seq_output_inversion] : Disables sequential output inversion

 

69 change_name命令：Changes the names of ports, cells, and nets in a design.

change_names [-rules name_rules] [-hierarchy] [-verbose] [-names_file names_file] [-log_changes log_file] [-restore] [-dont_touch object_list] [-instance instance] [-new_name new_name]

 

70 report_qor ：Displays QoR information and statistics for the current design. This command reports timing-path group and cell count details, along with current design statistics such as combinational, noncombinational, and total area. The command also reports static power, design rule violations, and compile-time details

 

71 report_constraint命令：Displays constraint-related information about a design.

report_constraint [-all_violators] [-verbose] [-significant_digits digits] [-max_area] [-max_delay] [-critical_range] [-min_delay] [-max_capacitance] [-min_capacitance] [-max_transition] [-max_fanout] [-cell_degradation] [-max_toggle_rate] [-min_porosity] [-max_dynamic_power] [-max_leakage_power] [-max_net_length] [-connection_class] [-multiport_net] [-nosplit] [-max_toggle_rate] [-max_total_power] [-min_pulse_width] [-scenarios scenario_list]

[-all_violators]：Displays a summary of all of the optimization and design rule constraints with violations in the current design.

[-verbose]：Displays more detail about constraint calculations.

[-significant_digits digits]：Specifies thenumberofdigitstotherightofthedecimalpointthatareto be reported.

 

72 Linux 的I/O重定向：通过文件的形式实现标准I/O流

< 标准输入重定向

> 覆盖方式标准输出重定向

>> 追加方式标准输出重定向

 

73 hdlin_enable_rtldrc_info :

Controls whether RTL TestDRC creates file name and line number information for HDL constructs and instances for designs processed by subsequent shell commands.

 

74 test_default_scan_style :

Defines the default insert_dft scan style, to use if a scan style is not specified using set_scan_style. The variable must identify a supported scan style; currently one of multiplexed_flip_flop, clocked_scan, lssd, aux_clock_lssd, combinational, or none. The default is multiplexed_flip_flop.

 

75 set_scan_configuration : Specifies the scan chain design.(man2)

 

76 test_default_delay : Defines the default time in a tester cycle to apply values to input ports

 

77 test_default_bidir_delay : Defines the default switching time of bidirectional ports in a tester cycle.

 

78 test_default_strobe : Defines the default strobe time in a test cycle for output ports and bidirectional ports in output mode.

 

79 test_default_period : Defines the length of a test vector cycle

 

80 set_dft_signal : Specifies the DFT signal types for DRC and DFT insertion.

set_dft_signal [-view existing_dft|spec] [-test_mode mode_name] -type signal_type [-port port_list] [-active_state active_state] [-timing timing] [-period period] [-hookup_pin hookup_pin] [-hookup_sense hookup_sense] [-internal_clocks none|single|multi] [-ctrl_bits ctrl_bits_list] [-pll_clock pll_clock] [-ate_clock ate_clock] [-differential_clock clock_port] [-connect_to pin_list] [-usage use_type] [-associated_internal_clocks clock_pins_list] [-associated_clock associated_clock] [-connect_to_domain_fall clock_names] [-connect_to_domain_rise clock_names] [-exclude cell_names]

[-view existing_dft | spec]: Indicates the view to which the specification applies. spec (the default value) implies that the specification refers to ports that the tool must use during DFT insertion.

[-port port_list]:Indicates the list of ports on which to apply the specifications

[-type signal_type ]Specifies the signal type. • ScanDataIn is one of the scan inputs of the design. • ScanDataOut is one of the scan outputs of the design.

[ -hookup_pin hookup_pin ]Identifies a specific pin to which wires are to be connected.

[-timing timing] Specifies the rise time and fall time for clocks.

[-active_state active_state ]Specifies the active states for the following signal types: ScanEnable Reset Constant TestMode pll_reset pll_bypass

 

81 set_dft_drc_configuration : Sets the DFT DRC configuration for the current design.

 

82 set_dft_insertion_configuration : Sets the DFT insertion configuration for the current design.

 

83 set_scan_state : Sets the scan state status for the current db design.

 

84 set_scan_element : set_scan_element true |false cell_design_ref_list

Sets the scan_element attribute on specified design objects, to determine whether insert_dft replaces them with scan cells.

85 create_test_protocol : Creates a test protocol based on user specifications.

 

86 dft_drc : Checks the current design against test design rules.

dft_drc [-pre_dft] [-verbose] [-coverage_estimate] [-sample percentage]

[-coverage_estimate] :Generates a test coverage estimate at the end of design rule checking.

[-verbose] : Controls the amount of detail when displaying violations. If specified, every violation instance is displayed.

 

87 report_dft_signal : Displays options specified by the set_dft_signal command.

report_dft_signal [-view spec|existing_dft] [-test_mode list_of_mode_names | all] [-port list_of_port_names] [-type signal_type]

[-view spec | existing_dft ] Specifies the view from which to report. Valid options are spec and existing_dft.

 

88 preview_dft : Previews, but does not implement, the test points, scan chains, and on-chip clocking control logic to be added to the current design.

 

89 compile_instance_name_prefix :Specifies the prefix used in generating cell instance names when the compile command is run.

 

90 insert_dft : Inserts DFT logic in the current design.

 

91 write_scan_def : Writes scan chain information in SCANDEF format for performing scan chain reordering using place and route tools.

 

92 report_scan_configuration : Displays options specified by the set_scan_configuration command.

 

93 report_scan_path : Displays scan paths and scan cells specified by the set_scan_path command and displays scan paths inserted by the insert_dft command.

 

94 write_test_protocol : Writes a STIL test protocol file.    

write_test_protocol [-design design_name] [-output file_name] [-test_mode mode_name] [-instruction instruction_name] [-names format_name]

 

95 write_sdc : Writes out a script in Synopsys Design Constraints (SDC) format.

write_sdc file_name [-nosplit] [-version sdc_version]

 

96 write_sdf : Writes a Standard Delay Format (SDF) back-annotation file.

 

97 report_area : Displays area information for the current design or instance

98 report_power : Calculates and reports dynamic and static power for the design or instance.