触摸屏的磨难
因为目前目标板上还没有USB主口，所以无法使用USB鼠标。所以触摸屏就成了唯一的输入设备，如果触摸不正常，就没有办法对WINCE系统进行设置，也就没有办法进行网络方面的调试。这实在是让silentmj感到无可奈何啊。。。
因为目前的注册表是没有保存到flash上的，所以掉电以后之前所做的设置都会丢失。
）让系统启动后运行程序
a）将touchcalstarter.exe复制到release目录下
b）修改release目录下的shell.reg,
---------------------------------------------------------------------
[HKEY_LOCAL_MACHINE\init]
"Launch50"="explorer.exe"
"Depend50"=hex:14,00, 1e,00
"Launch80"="touchcalstarter.exe"
"Depend80"=hex:32,00
---------------------------------------------------------------------
LauchXX的值就是应用程序的路径，XX用来表示期望的启动顺序，XX数值越小越靠前
DependXX的值表示应用程序所依赖的启动项的十六进制（低16位在前，高16位在后）
重新sysgen以后需要重新修改该文件，如果不想反复修改shell.reg
）TouchCalibrate不退出的解决办法
问题表现为依次点击完5个点之后，又重新从中间那个点开始
选到调试模式，总算发现了问题的所在：校准后的误差仍然太大，系统不认可
0x8394f494: calibrating 5 point set
0x8394f494: Maximum Allowed Error 5:
0x8394f494: Calibration Results:
0x8394f494: Screen => Mapped
0x8394f494: ( 320, 240) => ( 394, 244)
0x8394f494: ( 128, 96) => ( 73, 111)
0x8394f494: ( 128, 384) => ( 251, 343)
0x8394f494: ( 512, 384) => ( 384, 413)
0x8394f494: ( 512, 96) => ( 499, 89)
0x8394f494: Maximum error (square of Euclidean distance in screen units) = 17225
0x8394f494: Maximum error 17225 exceeds calibration threshold 5
在读帮助文档的时候，我认识到这个calibration threshold应该是被ErrorAnalysis函数所使用的，具体数值由MaxCalError来控制。如下注册表文件就把容许误差设置成了0x10。
[HKEY_LOCAL_MACHINE\HARDWARE\DEVICEMAP\TOUCH]
"DriverName"="touch.dll"
"MaxCalError"=dword:10
把容许误差调大以后校准程序便能够退出了。
）目标板触摸驱动程序分析
触摸-》ADS7843产生中断-》读取采样值，启动定时器-》定时从ADS7843读采样值
ADS7843工作在返回12位采样值的模式
tchpdd.cpp中与ADS7843的交互调用过程如下：
DdsiTouchPanelGetPoint
PddpTouchPanelEvaluateSamples ---->
SampleTouchScreen
Ads7843_Conversion
Ads7843_Write
Ads7843_Read
Touch_CoordinateConversion ---->
1: BOOL PddpEnablePenInterrupt(BOOL irqMode) 2: { 3: 4: if(irqMode==PEN_DOWN) // if next expected interrupt is pen down
5: { 6: Ads7843_Enable_IRQ(); 7: }8: else
9: { // Enable timer interrupt for drawing
10: enableTouchTimerInterrupt(TOUCH_TIMER_INCREMENT); 11: } 12: 13: return (TRUE);
14: } 15: 定时器的开启：
void enableTouchTimerInterrupt(unsigned timeout)
{
v_pOSTReg->osmr1 = v_pOSTReg->oscr + timeout; //当osmr1 == oscr,且oier相应位设置为允许时会产生中断
//allows a match between OSMR[1] and the OS Timer to assert interrupt bit M1 in the OSSR
*(unsigned int *)&v_pOSTReg->oier |= OIER_E1; //允许osmr1 == oscr 时产生中断
//enable the interrupt for OSMR1
*(unsigned int *)&v_pICReg->icmr |= ICMR_OSMR1;//允许osmr1所产生的中断
// OS timer match register 1 has matched the OS timer counter
*(unsigned int *)&v_pOSTReg->ossr = OSSR_M1; //清除OSSR中osmr1对应的match标志
}
oscr寄存器（P141，Developer’s Manual）
OS Timer Count Register (OSCR)
The OSCR, shown in Table 4-44, is a 32-bit counter that increments on rising edges of the
3.6864 MHz clock. This counter can be read or written at any time. It is recommended that the
system write-protect this register through the MMU protection mechanisms.
After the OSCR is written, there is a delay before the register is actually updated. Software must
make sure the register has changed to the new value before relying on the contents of the register.
oier寄存器（P140,DM）
OS Timer Interrupt Enable Register (OIER)
The OIER, shown in Table 4-42, contains four enable bits that indicate whether a match between
one of the match registers and the OS timer counter sets a status bit in the OSSR. Each match
register has a corresponding enable bit. Clearing an enable bit does not clear the corresponding
interrupt status bit if it is already set.
osmr寄存器（P139,DM）
These registers are 32-bits wide and are readable and writable by the processor. They are compared
against the OSCR after every rising edge of the 3.6864 MHz clock. If any of these registers match
the counter register, and the appropriate interrupt enable bit is set, then the corresponding status bit
in the OSSR is set. The status bits are routed to the interrupt controller where they can be unmasked
to cause a CPU interrupt. The OSMR3 can also be used as a watchdog timer.
Table 4-41 shows the bitmap of the OS Timer Match register. All four registers are identical, except
for location. A single, generic OS Timer match register is described, but all information is common
to all four OS Timer Match Registers.
ossr寄存器(P141,DM)
OS Timer Status Register (OSSR)
The OSSR, shown in Table 4-45, contains status bits that indicate a match has occurred between
any of the four match registers and the OSCR. These bits are set when the match event occurs
(following the rising edge of the 3.6864 MHz clock) and the corresponding interrupt enable bit is
set in the OIER. The OSSR bits are cleared by writing a one to the proper bit position. Writing
zeros to this register has no effect. Write all reserved bits as zeros and ignore all reads.
）MSDN
只好退回来看PB4.2带的帮助文件
说来惭愧，最近才首次比较认真读了《Driver Development》一节
WINCE42的分层驱动模型：
DDI—》MDD-》DDSI-》PDD
