关于ARM大小端模式和CPU有关还是编译器有关

结论，ARM大小端模式和CPU有关也和编译器有关系。

ARM默认状态配置为小端模式，编译器不指定编译模式也默认是小端模式。但有些ARM是可以配置为大端模式的。例如：

• ARMv7-A: In ARMv7-A, the mapping of instruction memory is always little-endian.
• ARMv7-R: SCTLR.IE, bit[31], that indicates the instruction endianness configuration.
• ARMv7-M: Armv7-M supports a selectable endian model in which, on a reset, a control input determines whether the endianness is big endian (BE) or little endian (LE). This endian mapping has the following restrictions: The endianness setting only applies to data accesses. Instruction fetches are always little endian. All accesses to the SCS are little endian, see System Control Space (SCS) on page B3-595.
• ARMv8-aarch32: aarch32: When using AArch32, having the CPSR.E bit have a different value to the equivalent System Control register EE bit when in EL1, EL2, or EL3 is now deprecated
• ARMv8-aarch64: aarch64: This data endianness is controlled independently for each Execution level. For EL3, EL2 and EL1, the relevant register of SCTLR_ELn.

如果在ARM上面配置了大端模式，gcc编译器则需要增加参数-mbig-endian

-mlittle-endian
Generate code for a processor running in little-endian mode. This is the default for all standard configurations.
-mbig-endian
Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.

与CPU配置保持一致。

参考文献：

https://gcc.gnu.org/onlinedocs/gcc-4.3.2/gcc/ARM-Options.html
https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/Endianness?lang=en
https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Endian-support/Instruction-endianness