2012年7月31日
android 4.1 Emulator Skins
摘要： 1 The downloadable platform includes the following emulator skins: 2 3 QVGA (240x320, low density, small screen) 4 WQVGA400 (240x400, low density, normal screen) 5 WQVGA432 (240x432, low density, normal screen) 6 HVGA (320x480, medium density, normal screen) 7 WVGA800 (480x800, high density, norma.. 阅读全文
posted @ 2012-07-31 21:19 IAmAProgrammer 阅读(139) 评论(0) 推荐(0) 编辑
stm32 sdio sdcard fatfs
摘要： 1 /****************************************Copyright (c)**************************************************** 2 ** 3 ** http://www.powermcu.com 4 ** 5 **--------------File Info--------------------------------------------------------------------------------- ... 阅读全文
posted @ 2012-07-31 14:41 IAmAProgrammer 阅读(3695) 评论(0) 推荐(0) 编辑
stm32 spi sdcard fatfs
摘要： 1 http://cba.si/stuff/fatfs_diskio_sdcard_spi.c 2 3 /* 4 * (c) Domen Puncer, Visionect, d.o.o. 5 * BSD License 6 * 7 * v0.2 add support for SDHC 8 */ 9 10 #include <stdio.h> 11 #include "stm32f10x_lib.h" 12 13 /* 14 * Code is split into 3 parts: 15 * - generic SPI ... 阅读全文
posted @ 2012-07-31 14:34 IAmAProgrammer 阅读(2395) 评论(0) 推荐(0) 编辑
FATFS Copy Files
摘要： 1 // 文件复制 2 // 将psrc文件,copy到pdst. 3 // psrc,pdst:源文件和目标文件 4 // fwmode:文件写入模式 5 // 0:不覆盖原有的文件 6 // 1:覆盖原有的文件 7 u8 mf_copy ( u8 * psrc, u8 * pdst, u8 fwmode ) 8 { 9 u8 res; 10 u16 br = 0; 11 u16 bw = 0; 12 FIL * fsrc = 0; 13 FIL * fdst = 0; 14 u8 * fbuf = 0; 15 fsrc ... 阅读全文
posted @ 2012-07-31 12:14 IAmAProgrammer 阅读(2718) 评论(0) 推荐(0) 编辑
2012年5月22日
xilinx spartan-3a oddr
摘要： 1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 16:05:33 05/21/2012 6 -- Design Name: 7 -- Module Name: oddr2_top - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Des... 阅读全文
posted @ 2012-05-22 19:04 IAmAProgrammer 阅读(422) 评论(0) 推荐(0) 编辑
xilinx spartan-3a iddr2 oddr2
摘要： 1 -- IDDR2: Input Double Data Rate Input Register with Set, Reset 2 -- and Clock Enable. 3 -- Spartan-3A 4 -- Xilinx HDL Language Template, version 14.1 5 6 IDDR2_inst : IDDR2 7 generic map( 8 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C... 阅读全文
posted @ 2012-05-22 19:03 IAmAProgrammer 阅读(2119) 评论(0) 推荐(0) 编辑
2012年5月21日
xilinx spartan-3a oddr2
摘要： 阅读全文
posted @ 2012-05-21 16:45 IAmAProgrammer 阅读(307) 评论(0) 推荐(0) 编辑
xilinx spartan-3a iob
摘要： 阅读全文
posted @ 2012-05-21 16:45 IAmAProgrammer 阅读(132) 评论(0) 推荐(0) 编辑
2012年5月20日
How To Set a Status Flag in One Clock Domain, Clear It in Another
摘要： http://www.floobydust.com/flancter/Flancter_App_Note.pdf 阅读全文
posted @ 2012-05-20 10:27 IAmAProgrammer 阅读(524) 评论(0) 推荐(0) 编辑
2012年5月16日
SPI Flash controller for DIY Calculator
摘要： 1 -- 2 -- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at) 3 -- 4 -- This program is free software; you can redistribute it and/or 5 -- modify it under the terms of the GNU General Public License 6 -- as published by the Free Software Foundation; either version 2 7 ... 阅读全文
posted @ 2012-05-16 12:28 IAmAProgrammer 阅读(726) 评论(0) 推荐(0) 编辑
Dual port RAM with enable on each port( vhdl )
摘要： 1 -- Dual port RAM with enable on each port 2 -- Xilinx rams_14 3 4 library ieee; 5 use ieee.std_logic_1164.all; 6 use ieee.std_logic_unsigned.all; 7 8 entity dp_ram is 9 port(clk : in std_logic;10 ena : in std_logic;11 enb : in std_logic;12 wea : in std_logic;13 add... 阅读全文
posted @ 2012-05-16 12:15 IAmAProgrammer 阅读(325) 评论(0) 推荐(0) 编辑
fifo vhdl
摘要： 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 5 entity fifo is 6 port ( 7 reset, clk, r, w : in std_logic; 8 empty, full : out std_logic; 9 d : in std_logic_vector(7 downto 0);10 q : out std_logic_vector(7... 阅读全文
posted @ 2012-05-16 12:11 IAmAProgrammer 阅读(428) 评论(0) 推荐(0) 编辑
SPI bus master for System09 (2)
摘要： 1 --===========================================================================-- 2 -- -- 3 -- Synthesizable Serial Peripheral Interface Master -- 4 -- ... 阅读全文
posted @ 2012-05-16 12:09 IAmAProgrammer 阅读(393) 评论(0) 推荐(0) 编辑
SPI bus master for System09
摘要： 1 -- SPI bus master for System09 2 -- (http://members.optushome.com.au/jekent/system09/index.html) 3 4 -- This core implements a SPI master interface. Transfer size is 4, 8, 12 or 5 -- 16 bits. The SPI clock is 0 when idle, sampled on the rising edge of the SPI 6 -- clock. The SPI clock ... 阅读全文
posted @ 2012-05-16 12:06 IAmAProgrammer 阅读(320) 评论(0) 推荐(0) 编辑
VSPI core implements an SPI interface
摘要： 1 ------------------------------------------------------------------------ 2 -- Copyright 1997-1998 VAutomation Inc. Nashua NH USA. 3 -- Visit HTTP://www.vautomation.com for mor details on our other 4 -- Synthesizable microprocessor and peripheral cores. 5 -- 6 -- This program is free s... 阅读全文
posted @ 2012-05-16 12:05 IAmAProgrammer 阅读(375) 评论(0) 推荐(0) 编辑
spi master vhd timing
摘要： 阅读全文
posted @ 2012-05-16 12:00 IAmAProgrammer 阅读(227) 评论(0) 推荐(0) 编辑
spi master vhd
摘要： 1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: shangdawei@gmail.com 4 -- 5 -- Create Date: 08:46:25 05/12/2012 6 -- Design Name: 7 -- Module Name: spi_master - Behavioral 8 -- Project Name: 9 -- Target Dev... 阅读全文
posted @ 2012-05-16 11:51 IAmAProgrammer 阅读(457) 评论(0) 推荐(1) 编辑
altera cpld spi master verilog
摘要： 1 /*********************************************************************************************** 2 * SPI MASTER 3 * January 2007 4 ************************************************************************************************/ 5 `timescale 10ns/1ns 6 module SPI_Master ( miso, mosi, sclk, ... 阅读全文
posted @ 2012-05-16 10:19 IAmAProgrammer 阅读(2841) 评论(0) 推荐(1) 编辑
2012年5月15日
同步复位与异步复位-异步复位和同步复位区别.
摘要： 同步复位与异步复位-异步复位和同步复位区别..浏览:188次 一、同步复位与异步复位特点： 同步复位就是指复位信号只有在时钟上升沿到来时，才能有效。否则，无法完成对系统的复位工作。 异步复位是指无论时钟沿是否到来，只要复位信号有效，就对系统进行复位。 二、异步复位和同步复位的优缺点： 1、同步复位的优点大概有3条： a、有利于仿真器的仿真。 b、可以使所设计的系统成为100%的同步时序电路，这便大大有利于时序分析，而且综合出来的fmax一般较高。 c、因为他只有在时钟有效电平到来时才有效，所以可以滤除高于时钟频率的毛刺。同步复位的缺点： a、复位信号的有效时长必须大于时... 阅读全文
posted @ 2012-05-15 15:53 IAmAProgrammer 阅读(3369) 评论(0) 推荐(0) 编辑
2012年5月14日
spi master vhdl
摘要： 1 http://eewiki.net/display/LOGIC/Serial+Peripheral+Interface+(SPI)+Master+(VHDL) 2 3 -------------------------------------------------------------------------------- 4 -- 5 -- FileName: spi_master.vhd 6 -- Dependencies: none 7 -- Design Software: Quartus II Version 9.0 B... 阅读全文
posted @ 2012-05-14 10:20 IAmAProgrammer 阅读(1181) 评论(0) 推荐(1) 编辑
2012年5月13日
Using real data types in VHDL
摘要： 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.MATH_REAL.ALL; 4 5 entity real_demo is 6 end real_demo; 7 8 architecture Behavioral of real_demo is 9 10 --signals declared with the REAL data type.11 --MATH_PI is a constant defined in the math_real package.12 signal X : real := -MATH_PI/... 阅读全文
posted @ 2012-05-13 12:34 IAmAProgrammer 阅读(460) 评论(0) 推荐(0) 编辑
uart baud rate generator
摘要： library IEEE;use IEEE.std_logic_1164.all;use IEEE.NUMERIC_STD.all;library unisim;use unisim.vcomponents.all;entity uart_brg is port ( i_clock : in std_logic; i_prescale : in unsigned (3 downto 0); i_divisor : in unsigned (7 downto 0); i_fraction : in unsigned (3 ... 阅读全文
posted @ 2012-05-13 11:37 IAmAProgrammer 阅读(584) 评论(0) 推荐(0) 编辑
2012年5月12日
Description of syntax for IF, CASE, WITH and WHEN
摘要： 1 -- ============================================================================= 2 -- file name is: mux4_1.vhd (mux=multiplexer) 3 -- Author: Kim Petersen 4 -- Created: 00.04.10 last modified: 00.04.13 5 -- ============================================================... 阅读全文
posted @ 2012-05-12 21:36 IAmAProgrammer 阅读(290) 评论(0) 推荐(0) 编辑
srl16e verilog
摘要： 1 module SRL16E(Q, A0, A1, A2, A3, CLK, D, CE); 2 3 input A0, A1, A2, A3, CLK, D, CE; 4 output Q; 5 6 reg[15:0] shift_reg; 7 reg Q; 8 9 always@(posedge CLK)10 begin11 if (CE)12 shift_reg <= {shift_reg[14:0],D};13 end14 15 always @(A3 or A2 or A1 or A0 or shift_reg)16 begin17 18 case({A3,... 阅读全文
posted @ 2012-05-12 20:33 IAmAProgrammer 阅读(746) 评论(0) 推荐(0) 编辑
2012年5月11日
vhdl uart
摘要： 1 ------------------------------------------------------- 2 -- Design Name : uart_vhdl 3 -- File Name : uart_vhdl.vhd 4 -- Function : Simple UART 5 -- Coder : Deepak Kumar Tala (Verilog) 6 -- Translator : Alexander H Pham (VHDL) 7 ------------------------------------------------... 阅读全文
posted @ 2012-05-11 13:38 IAmAProgrammer 阅读(679) 评论(0) 推荐(0) 编辑
2012年5月10日
vhdl 状态机
摘要： 4-State Mealy State MachineThe outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.4-State Moore State MachineThe outputs of a Moore state machine depend only on the present state. The outp 阅读全文
posted @ 2012-05-10 23:28 IAmAProgrammer 阅读(699) 评论(0) 推荐(0) 编辑
How can I discribe a ROM in VHDL
摘要： 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity single_port_rom is 6 7 port 8 ( 9 addr : in natural range 0 to 255;10 clk : in std_logic;11 q : out std_logic_vector(7 downto 0)12 );13 14 end entity;15 16 architecture rtl of single_port_r... 阅读全文
posted @ 2012-05-10 23:21 IAmAProgrammer 阅读(629) 评论(0) 推荐(0) 编辑
VHDL 整数 小数 分数 分频
摘要： 1 --Description: 带复位功能的加法计数器 2 library IEEE; 3 use IEEE.STD_LOGIC_1164.ALL; 4 use IEEE.STD_LOGIC_ARITH.ALL; 5 use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 7 entity ripple is 8 generic (width: integer := 4); 9 port( clk, rst: in std_logic;10 cnt: out std_logic_vector(width - 1 downto 0));11 end r... 阅读全文
posted @ 2012-05-10 20:01 IAmAProgrammer 阅读(1642) 评论(0) 推荐(0) 编辑
source file for the Image Package image_pkg
摘要： 1 ----------------------------------------------------------------- 2 -- Copyright (c) 1997 Ben Cohen. All rights reserved. 3 -- This model can be used in conjunction with the Kluwer Academic books 4 -- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 5 -- "VHDL Amswers to 阅读全文
posted @ 2012-05-10 19:30 IAmAProgrammer 阅读(485) 评论(0) 推荐(0) 编辑
The Dual-Modulus Divider in VHDL
摘要： http://www.edn.com/contents/images/6372832.pdf 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity example_dual_mod is 5 port( 6 reset : in std_logic; -- Active-High Synchronous Reset 7 clock : in std_logic; -- Input Clock 8 output : out std_logic -- Output Baud Clock 9 )... 阅读全文
posted @ 2012-05-10 19:28 IAmAProgrammer 阅读(482) 评论(0) 推荐(0) 编辑
synthesisable VHDL for a fixed ratio frequency divider
摘要： http://fractional-divider.tripod.com/ 1 -------------------------------------------------------------------------------- 2 -- File : fracn20.vhd 3 -- Contains : entity fracn20 (architecture rtl) 4 -- Author : Allan Herriman 5 -- Date : Tue Dec 24 2002 6 -- Version ... 阅读全文
posted @ 2012-05-10 19:22 IAmAProgrammer 阅读(1423) 评论(0) 推荐(0) 编辑
Dual-Port Block RAM with Two Write Ports and Byte-wide Write Enable in Read-First Mode
摘要： Initializing Block RAM from external intel hex file 1 -- 2 -- Dual-Port Block RAM with Two Write Ports and 3 -- Byte-wide Write Enable in Read-First Mode 4 -- 5 -- Initializing Block RAM from external intel hex file 6 -- 7 -- http://www.keil.com/support/docs/1584/ 8 ------------------------... 阅读全文
posted @ 2012-05-10 13:58 IAmAProgrammer 阅读(663) 评论(0) 推荐(0) 编辑
A small-to-medium depth FIFO base FIFO_RBU
摘要： 1 ------------------------------------------------------------------------------- 2 -- Filename: fifo.vhd 3 -- 4 -- Description: 5 -- A small-to-medium depth FIFO. 6 -- For data storage, the SRL elements native to the target FGPA family are used. 7 -- If the FIFO depth exceeds the available ... 阅读全文
posted @ 2012-05-10 13:57 IAmAProgrammer 阅读(284) 评论(0) 推荐(0) 编辑
A small-to-medium depth FIFO with optional capability to back up and reread data
摘要： 1 ------------------------------------------------------------------------------- 2 -- Filename: fifo_rbu.vhd 3 -- 4 -- Description: 5 -- A small-to-medium depth FIFO with optional capability to back up and reread data. 6 -- For data storage, the SRL elements native to the target FGPA famil... 阅读全文
posted @ 2012-05-10 13:56 IAmAProgrammer 阅读(301) 评论(0) 推荐(0) 编辑
This counter can increment, decrement or skip ahead by an arbitrary amount
摘要： 1 ------------------------------------------------------------------------------- 2 -- Filename: inc_dec_addn_cntr.vhd 3 -- 4 -- Description: This counter can increment, decrement or skip ahead 5 -- by an arbitrary amount. 6 -- 7 -- If Reset is active, t... 阅读全文
posted @ 2012-05-10 13:55 IAmAProgrammer 阅读(247) 评论(0) 推荐(0) 编辑
dynamic_shift_reg SRL16E
摘要： 1 ------------------------------------------------------------------------------- 2 -- Filename: dynamic_shift_reg.vhd 3 -- 4 -- Description: This module implements a dynamic shift register with clock 5 -- enable. (Think, for example, of the function of the SRL16E.) 6 --... 阅读全文
posted @ 2012-05-10 13:55 IAmAProgrammer 阅读(451) 评论(0) 推荐(0) 编辑
Parametrilayze based on SRL16 shift register FIFO
摘要： 1 ------------------------------------------------------------------------------- 2 -- Title : Parametrilayze based on SRL16 shift register FIFO 3 -- Project : 4 ------------------------------------------------------------------------------- 5 -- File : fifo_srl_uni.vhd 6 -- Au... 阅读全文
posted @ 2012-05-10 13:53 IAmAProgrammer 阅读(533) 评论(0) 推荐(0) 编辑
LUT4/MUXF5/MUXF6 logic : Multiplexer 8:1
摘要： 1 1 // how do I get MUXF5/MUXF6. 2 2 // This implies eight to one multiplexing, so use a three bit select in the case statement. 3 3 // This following will produce the LUT4/MUXF5/MUXF6 logic: 4 4 5 5 module lut_test8(a, b, c, f, s); 6 6 input[3:0]a, b; 7 7 input[1:0]s; 8 8 input[1:0]f; ... 阅读全文
posted @ 2012-05-10 13:52 IAmAProgrammer 阅读(686) 评论(0) 推荐(0) 编辑
srl16e fifo verilog
摘要： 1 module srl16e_fifo ( clk, datain, wr, dataout, rd, fullness); 2 parameter WIDTH = 8; 3 4 input clk; 5 input [WIDTH-1:0] datain; 6 input wr; 7 output [WIDTH-1:0] dataout; 8 input rd; 9 output reg [4:0] fullness;10 11 always @(posedge clk)12 begin13 fullness <= (fullness + wr... 阅读全文
posted @ 2012-05-10 13:51 IAmAProgrammer 阅读(720) 评论(0) 推荐(0) 编辑
Bucket Brigade FIFO SRL16E ( VHDL )
摘要： View Code 1 -- 'Bucket Brigade' FIFO 2 -- 16 deep 3 -- 8-bit data 4 -- 5 -- Version : 1.10 6 -- Version Date : 3rd December 2003 7 -- Reason : '--translate' directives changed to '--synthesis translate' directives 8 -- 9 -- Version : 1.00 10 -- Version Date : 14th October 200 阅读全文
posted @ 2012-05-10 12:33 IAmAProgrammer 阅读(516) 评论(0) 推荐(0) 编辑