摘要：
1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 16:05:33 05/21/2012 6 -- Design Name: 7 -- Module Name: oddr2_top - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Des... 阅读全文
摘要：
1 -- IDDR2: Input Double Data Rate Input Register with Set, Reset 2 -- and Clock Enable. 3 -- Spartan-3A 4 -- Xilinx HDL Language Template, version 14.1 5 6 IDDR2_inst : IDDR2 7 generic map( 8 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C... 阅读全文