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1 -- 2 -- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at) 3 -- 4 -- This program is free software; you can redistribute it and/or 5 -- modify it under the terms of the GNU General Public License 6 -- as published by the Free Software Foundation; either version 2 7 ... 阅读全文
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1 -- Dual port RAM with enable on each port 2 -- Xilinx rams_14 3 4 library ieee; 5 use ieee.std_logic_1164.all; 6 use ieee.std_logic_unsigned.all; 7 8 entity dp_ram is 9 port(clk : in std_logic;10 ena : in std_logic;11 enb : in std_logic;12 wea : in std_logic;13 add... 阅读全文
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1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 5 entity fifo is 6 port ( 7 reset, clk, r, w : in std_logic; 8 empty, full : out std_logic; 9 d : in std_logic_vector(7 downto 0);10 q : out std_logic_vector(7... 阅读全文
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1 --===========================================================================-- 2 -- -- 3 -- Synthesizable Serial Peripheral Interface Master -- 4 -- ... 阅读全文
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1 -- SPI bus master for System09 2 -- (http://members.optushome.com.au/jekent/system09/index.html) 3 4 -- This core implements a SPI master interface. Transfer size is 4, 8, 12 or 5 -- 16 bits. The SPI clock is 0 when idle, sampled on the rising edge of the SPI 6 -- clock. The SPI clock ... 阅读全文
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1 ------------------------------------------------------------------------ 2 -- Copyright 1997-1998 VAutomation Inc. Nashua NH USA. 3 -- Visit HTTP://www.vautomation.com for mor details on our other 4 -- Synthesizable microprocessor and peripheral cores. 5 -- 6 -- This program is free s... 阅读全文
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1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: shangdawei@gmail.com 4 -- 5 -- Create Date: 08:46:25 05/12/2012 6 -- Design Name: 7 -- Module Name: spi_master - Behavioral 8 -- Project Name: 9 -- Target Dev... 阅读全文
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1 /*********************************************************************************************** 2 * SPI MASTER 3 * January 2007 4 ************************************************************************************************/ 5 `timescale 10ns/1ns 6 module SPI_Master ( miso, mosi, sclk, ... 阅读全文