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4-State Mealy State MachineThe outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.4-State Moore State MachineThe outputs of a Moore state machine depend only on the present state. The outp 阅读全文
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1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity single_port_rom is 6 7 port 8 ( 9 addr : in natural range 0 to 255;10 clk : in std_logic;11 q : out std_logic_vector(7 downto 0)12 );13 14 end entity;15 16 architecture rtl of single_port_r... 阅读全文
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1 --Description: 带复位功能的加法计数器 2 library IEEE; 3 use IEEE.STD_LOGIC_1164.ALL; 4 use IEEE.STD_LOGIC_ARITH.ALL; 5 use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 7 entity ripple is 8 generic (width: integer := 4); 9 port( clk, rst: in std_logic;10 cnt: out std_logic_vector(width - 1 downto 0));11 end r... 阅读全文
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1 ----------------------------------------------------------------- 2 -- Copyright (c) 1997 Ben Cohen. All rights reserved. 3 -- This model can be used in conjunction with the Kluwer Academic books 4 -- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 5 -- "VHDL Amswers to 阅读全文
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http://www.edn.com/contents/images/6372832.pdf 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity example_dual_mod is 5 port( 6 reset : in std_logic; -- Active-High Synchronous Reset 7 clock : in std_logic; -- Input Clock 8 output : out std_logic -- Output Baud Clock 9 )... 阅读全文
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http://fractional-divider.tripod.com/ 1 -------------------------------------------------------------------------------- 2 -- File : fracn20.vhd 3 -- Contains : entity fracn20 (architecture rtl) 4 -- Author : Allan Herriman 5 -- Date : Tue Dec 24 2002 6 -- Version ... 阅读全文
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Initializing Block RAM from external intel hex file 1 -- 2 -- Dual-Port Block RAM with Two Write Ports and 3 -- Byte-wide Write Enable in Read-First Mode 4 -- 5 -- Initializing Block RAM from external intel hex file 6 -- 7 -- http://www.keil.com/support/docs/1584/ 8 ------------------------... 阅读全文
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1 ------------------------------------------------------------------------------- 2 -- Filename: fifo.vhd 3 -- 4 -- Description: 5 -- A small-to-medium depth FIFO. 6 -- For data storage, the SRL elements native to the target FGPA family are used. 7 -- If the FIFO depth exceeds the available ... 阅读全文
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1 ------------------------------------------------------------------------------- 2 -- Filename: fifo_rbu.vhd 3 -- 4 -- Description: 5 -- A small-to-medium depth FIFO with optional capability to back up and reread data. 6 -- For data storage, the SRL elements native to the target FGPA famil... 阅读全文
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1 ------------------------------------------------------------------------------- 2 -- Filename: inc_dec_addn_cntr.vhd 3 -- 4 -- Description: This counter can increment, decrement or skip ahead 5 -- by an arbitrary amount. 6 -- 7 -- If Reset is active, t... 阅读全文
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1 ------------------------------------------------------------------------------- 2 -- Filename: dynamic_shift_reg.vhd 3 -- 4 -- Description: This module implements a dynamic shift register with clock 5 -- enable. (Think, for example, of the function of the SRL16E.) 6 --... 阅读全文
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1 ------------------------------------------------------------------------------- 2 -- Title : Parametrilayze based on SRL16 shift register FIFO 3 -- Project : 4 ------------------------------------------------------------------------------- 5 -- File : fifo_srl_uni.vhd 6 -- Au... 阅读全文
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1 1 // how do I get MUXF5/MUXF6. 2 2 // This implies eight to one multiplexing, so use a three bit select in the case statement. 3 3 // This following will produce the LUT4/MUXF5/MUXF6 logic: 4 4 5 5 module lut_test8(a, b, c, f, s); 6 6 input[3:0]a, b; 7 7 input[1:0]s; 8 8 input[1:0]f; ... 阅读全文
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1 module srl16e_fifo ( clk, datain, wr, dataout, rd, fullness); 2 parameter WIDTH = 8; 3 4 input clk; 5 input [WIDTH-1:0] datain; 6 input wr; 7 output [WIDTH-1:0] dataout; 8 input rd; 9 output reg [4:0] fullness;10 11 always @(posedge clk)12 begin13 fullness <= (fullness + wr... 阅读全文
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View Code 1 -- 'Bucket Brigade' FIFO 2 -- 16 deep 3 -- 8-bit data 4 -- 5 -- Version : 1.10 6 -- Version Date : 3rd December 2003 7 -- Reason : '--translate' directives changed to '--synthesis translate' directives 8 -- 9 -- Version : 1.00 10 -- Version Date : 14th October 200 阅读全文