LPC43xx SGPIO DMA and Interrupts
The SGPIO output pins SGPIO14 and SGPIO15 can trigger a GPDMA request
SGPIO pins SGPIO14 and SGPIO15 can trigger a GPDMA request. < Output = '1' >
To generate the request, program a pulse in the bit stream of slice 14 or 15.
For example, use a pattern like 0x4000 0000.
GPDMA Master 1 can access memories and peripherals
GPDMA master 0 can access memories and the SGPIO
The SGPIO interrupts<4> is connected to interrupt slot <Interrupt ID> #31 in the ARM Cortex-M4
The SGPIO interrupts<4> is connected to interrupt slot <Interrupt ID> #19 in the ARM Cortex-M0APP
The SGPIO Input Bit Match interrupt is connected to interrupt slot <Interrupt ID> #4 in the ARM Cortex-M0SUB
The SGPIO Data Pattern Match interrupt is connected to interrupt slot <Interrupt ID> #5 in the ARM Cortex-M0SUB
The SGPIO Shfit Clock interrupt is connected to interrupt slot <Interrupt ID> #6 in the ARM Cortex-M0SUB
The SGPIO Capture Clock interrupt is connected to interrupt slot <Interrupt ID> #7 in the ARM Cortex-M0SUB
SGPIO interrupt specific registers
For these interrupt specific registers, replace the x with the correct number for the interrupt.
- 0 for shift clock;
- 1 for capture clock, main register and shadow register exchange;
- 2 for data pattern match and
- 3 for input bit match.
4.3.1 CLR_EN_x
This register is used to disable interrupts.
Slice interrupts can be disabled by writing a 1 to the register.
For example, if a 1 is written to bit 2 the interrupt for slice C will be disabled.
4.3.2 SET_EN_x
This register is used to enable interrupts.
Slice interrupts can be enabled by writing a 1 to the register.
If, for example, a 1 is written to bit 3 the interrupt for slice D will be enabled.
4.3.3 ENABLE_x
Reading out this register will return what slices have their interrupts enabled.
If this register contains the value 0b1001 that means slice A and D have the interrupts enabled.
4.3.4 STATUS_x
Reading out this register will return on which slices an interrupt has happened.
It is possible that an interrupt happens on multiple slices at the same time.
If this register contains the value 0b1000100 interrupts happened on slice C and G.
4.3.5 CLR_STAT_x
This register is used to clear the interrupt state.
It is recommended to clear all interrupt states after handling the interrupts
otherwise the value in the STATUS_x register will also contain old interrupt states.
4.3.6 SET_STAT_x
This register is used to set interrupt states.
When a 1 is written to bit 0 it will look like an interrupt happened on slice A.
This register can be used for code testing.
SGPIO Interrupts
There are four interrupt methods available for SGPIO, they are:
- 1. On shift clock
- 2. On data exchange clock
- 3. On data pattern match
- 4. On input bit match (rising/falling edge, high/low level)
6.1 On shift clock
When enabled through SET_EN, this interrupt occurs every time COUNTx == 0.
This normally happens every time 1 data bit is clocked out or in of an SGPIO slice and can be CPU intensive. The registers used for this interrupt are:
• CLR_EN_0
• SET_EN_0
• ENABLE_0
• STATUS_0
• CTR_STATUS_0
• SET_STATUS_0
6.2 On data exchange (swap) clock
When enabled through SET_EN, this interrupt will occur every time the data
between the Data register (REGx) and the shadow register (REG_SSx) is exchanged. < POS == 0 >
This interrupt can be used to place new data in the shadow register,
at the next exchange (and interrupt) the new data will be loaded in the data register
and new data can be put in the shadow register.
The registers used for this interrupt are:
• CLR_EN_1
• SET_EN_1
• ENABLE_1
• STATUS_1
• CTR_STATUS_1
• SET_STATUS_1
6.3 On data pattern match < 1 or more bits match REG_SS >
It is possible to interrupt when a certain pattern is clocked in or out.
Slices A, I, H and P also support mask functionality for the pattern match interrupt.
The pattern match interrupt can be used to look for certain data when making a logic or data analyzer.
To use this interrupt, bit 0 from register SLICE_MUX_CFGx must be high. The MATCH_MODE bit must be set to 1.
The pattern can be up to 32-bit long and should program in REG_SS register.
If the data in the data register matches the data in the shadow register an interrupt will happen.
1) As long as this interrupt is enabled and 2) bit 0 in SLICE_MUX_CFGx is high the data register and shadow register will not swap.
The registers used for this interrupt are:
• CLR_EN_2
• SET_EN_2
• ENABLE_2
• STATUS_2
• CTR_STATUS_2
• SET_STATUS_2
6.4 On input bit match
When enabled through SET_EN, it is possible to interrupt on a low or high level or on a falling or rising edge on the input data bit.
The registers used for this interrupt are:
• CLR_EN_3
• SET_EN_3
• ENABLE_3
• STATUS_3
• CTR_STATUS_3
• SET_STATUS_3
