线性稳压器的基本类型
线性电压稳压器的分类
线性电压稳压器是按照导通组件技术进行分类，包括：
NPN-Darlington、NPN、PNP、PMOS 及 NMOS 稳压器。
表 1 显示不同的类型以及一般最小电压差与静态电流特性。
PNP 双极体晶体管一般被运用于低压降的应用，主要是因为这类晶体管很容易就能够达到低压降，
然而，它会产生高静态电流，而且效率不高，因此不适用于以发挥最高效率为首要考虑的应用。
PMOS 装置经过大量心力的开发，目前的效能已超越大多数的双极体装置。
NMOS 导通组件的最大优势是它的电阻不高，不过，闸极驱动的困难却使得这类导通组件在应用中显得并不理想。
NMOS LDO （如TPS74901）能够在 3A 输出电流的情况下达到 120mV 最小电压差。
与 PMOS 拓朴装置不同的是，输出电容器对于回路稳定性的影响不大。
不论是搭配多颗电容器或甚至不搭配电容器，德州仪器推出的多款 NMOS LDO 都能稳定的运作。
NMOS的瞬时响应也优于 PMOS 拓朴，对于低输入电压的应用更是如此。
Circuit Operation:
The load current is sensed by the "I SENSE" resistor, which develops a voltage that is directly related to the current.
This voltage is level shifted (and amplified) by the differential amplifier.
The voltage at the output of the differential amplifier is a ground-referenced signal that is proportional to the load current.
This "load current" signal coming from the differential amplifier is applied to the inverting input of the current limit error amplifier,
while the non-inverting input is connected to a reference voltage.
The value of this reference voltage would be equal to the voltage at the output of the differential amplifier
when the regulator is driving maximum current (at the current limit point).
Note that as long as the load current is below the limit threshold, the output of the current error amplifier is high
(and the voltage error amplifier keeps the regulator in constant voltage mode).
When the load current reaches the limit threshold, the output of the current error amplifier drops low
and starts sinking current away from the output of the voltage error amplifier (this puts the regulator in constant current mode).
When current limiting occurs, the regulator output voltage will drop below its nominal value,
which will be sensed by the voltage error amplifier as an undervoltage condition.
The voltage error amplifier will drive its output high in an attempt to raise the output voltage,
but the current error amplifier can sink all of the current coming from the voltage error amplifier.
Like the thermal limiter, the current limiter overrides the voltage error amplifier to prevent damage to the IC.
The load line shown in Figure 8 illustrates how the output voltage is held constant up to the point where the load current reaches the limit value,
where the regulator crosses over into constant current mode.
When operating in constant current mode, the IC regulates the load current to the "limit" value,
which means the output voltage may be any value down to zero volts.
It should be made clear that the thermal limiter can always override the current limiter,
and can reduce the output voltage and current to any value necessary to maintain a junction temperature of about 160°C.
For example, if the LP2952 (which is rated for 250 mA) is shorted from the output to ground,
a current will flow from the output which is greater than 250 mA but less than 530 mA (see "Current Limit specification on the data sheet).
However, if the input voltage is high enough to generate sufficient power to activate the thermal limiter,
that current will drop off as the LP2952 regulates its die temperature to about 160°C.
Important:
Current limit circuits are (by necessity) very high-speed circuits, and input bypass capacitors on the regulator
are always recommended to prevent possible device failure due to interaction with the input source impedance.
Super beta PNP Circuitry
The simplified schematic diagram of Micrel’s medium and high current monolithic LDOs appears as Figure 4-1.
The high current path from input to output through the pass transistor is in bold.
The bandgap reference and all other circuitry is powered via the Enable Circuit, which allows for “zero” current draw when disabled.
The reference voltage is compared to the sampled output voltage fed back by R1 and R2.
If this voltage is less than the bandgap reference, the op amp output increases.
This increases the current through driver transistor Q2, which pulls down on the base of Q1, turning it on harder.
If Q1’s base current rises excessively, the voltage drop across R3 enables Q3, which in turn limits the current through Q2.
Die temperature is monitored, and if it becomes excessive, the thermal shutdown circuit activates, clamping the base of Q2 and shutting down Q1.
The flag circuit looks at the output voltage sample and compares it to a reference set 5% lower.
If the sample is even lower, the flag comparator saturates the open collector flag transistor, signaling the fault condition.
Dropout Voltage
The Super beta PNP family of low-dropout regulators offers typical dropout voltages of only 300mV across the output current range.
This low dropout is achieved by using large and efficient multicelled PNP output transistors, and operating them in their highbeta range well below their capacity.
Dropout voltage in the Super beta PNP regulators is determined by the saturation voltage of the PNP pass element.
As in all bipolar transistors, the saturation voltage is proportional to the current through the transistor.
At light loads, the dropout voltage is only a few tens of millivolts. At moderate output currents, the dropout rises to 200 to 300mV.
At the full rated output, the typical dropout voltage is approximately 300mV for most of the families.
Lower cost versions have somewhat higher dropout at full load, generally in the 400 to 500mV range.
The data sheet for each device graphs typical dropout voltage versus output current.
Ground Current
Micrel’s Super beta PNP process allows these high current devices to maintain very high transistor beta—on the order of 100 at their full rated current.
This contrasts with competitive PNP devices that suffer with betas in the 10 to 30 range. This impacts regulator designs by reducing wasteful ground current.
Micrel’s beta of 100 translates into typical full load ground currents of only 1% of your output.
The data sheet for each device graphs typical ground current versus output current.
When linear regulators approach dropout, generally due to insufficient input voltage, base drive to the pass transistor increases to fully saturate the transistor.
With some older PNP regulators, the ground current would skyrocket as dropout approached.
Micrel’s Super beta PNP regulators employ saturation detection circuitry which limits base drive when dropout-induced saturation occurs, limiting ground current.
Fully Protected
Micrel regulators are survivors. Built-in protection features like current limiting, overtemperature shutdown, and reversed-input polarity protection allow LDO survival under otherwise catastrophic situations.
Other protection features are optionally available, such as overvoltage shutdown and a digital error flag.
Current Limiting
Current limiting is the first line of defense for a regulator.
It operates nearly instantaneously in the event of a fault, and keeps the internal transistor, its wire bonds,
and external circuit board traces from fusing in the event of a short circuit or extremely heavy output load.
The current limit operates by linearly clamping the output current in case of a fault.
For example, if a MIC29150 with a 2A current limit encounters a shorted load, it will pass up to 2A of current into that load.
The resulting high power dissipation (2A multiplied by the entire input voltage) causes the regulator’s die temperature to rise,
triggering the second line of defense, overtemperature shutdown.
Overtemperature Shutdown
As the output fault causes internal dissipation and die temperature rise, the regulator approaches its operating limits.
At a predetermined high temperature, the regulator shuts off its pass element, bringing output current and power dissipation to zero.
The hot die begins cooling. When its temperature drops below an acceptable temperature threshold, it automatically re-enables itself.
If the load problem has been addressed, normal operation resumes.
If the short persists, the LDO will begin sourcing current, will heat up, and eventually will turn off again.
This sequence will repeat until the load is corrected or input power is removed.
Although operation at the verge of thermal shutdown is not recommended,
Micrel has tested LDOs for several million ON/OFF thermal cycles without undue die stress.
In fact, during reliability testing, regulators are burned-in at the thermal shutdown-cycle limit.
Reversed Input Polarity
Protection from reversed input polarity is important for a number of reasons.
Consumer products using LDOs with this feature survive batteries inserted improperly or the use of the wrong AC adapter.
Automotive electronics must survive improper jump starting.
All types of systems should last through initial production testing with an incorrectly inserted (backward) regulator.
By using reversed input protected regulators, both the regulator and its load are protected against reverse polarity, which limits reverse current flow.
Overvoltage Shutdown
Most Micrel LDOs feature overvoltage shutdown.
If the input voltage rises above a certain predetermined level, generally between 35V and 40V, the control circuitry disables the output pass transistor.
This feature allows the regulator to reliably survive high voltage (60V or so—see the device data sheet for the exact limit) spikes on the input regardless of output load conditions.
The automotive industry calls this feature “Load-Dump Protection”1 and it is crucial to reliability in automotive electronics.
Many of Micrel’s regulator families offer a version with a digital error flag output.
The error flag monitors the output voltage and pulls its open collector (or drain) output low if the voltage is too low.
The definition of “too low” ranges from about –5% to –8% below nominal output, depending upon the device type.
The flag comparator is unaffected by low input voltage
or a too-light or too-heavy load (although a too-heavy load generally will cause the output voltage to drop, triggering the flag).
The most attractive device for the external pass element is the N-channel power MOSFET (see Figure 4-5).
Discrete N-channel MOSFET prices continue to decrease (due to high volume usage),
and the race for lower and lower ON resistance works in your favor.
The N-channel MOSFET, like the P-channel MOSFET, reduces ground current.
With device ON resistance now below 10mW, dropout voltages below 100mV are possible with output currents in excess of 10A.
Even lower dropouts are possible by using two or more pass elements in parallel.
Unfortunately, full gate-to-source enhancement of the N-channel MOSFET
requires an additional 10V to 15V above the required output voltage.
Controlling the MOSFET’s gate using a second higher voltage supply requires additional circuitry and is clumsy at best.
“线性”串联稳压器（见图1）通常包括一个基准电压源、一个比例输出电压与基准电压比较环节、
一个反馈放大器和一个串联调整管组成（双极型晶体管或FET 管）组成，用放大器控制稳压器的压降维持要求的输出电压值。
例如，如果负载电流下降，会引起输出电压显着上升，误差电压增大，
放大器的输出上升，调整管两端的电压会增加，因此输出电压回到其原始值。
图1 基本的增强型PMOS LDO
在图1中，误差放大器和PMOS晶体管构成压控电流源。
输出电压VOUT按分压比（R1，R2）成比例下降，并且将其与基准电压（VREF）比较。
误差放大器的输出控制增强型PMOS晶体管。
稳压器的“压差”是指输出电压与输入电压之间的压差，
如果此输入电压继续减小那么该电路便不能稳压。
通常认为当输出电压下降到低于标称值100 mV时是达到的目标。
表征这LDO稳压器的关键指标取决于负载电流和调整管的PN结温度。
压差对稳压器分为三类：标准稳压器、准LDO和LDO 。
标准稳压器，通常使用NPN调整管，通常输出管的压降大约为2V。
准LDO稳压器，通常使用达林顿复合管结构（见图2）以便实现由一只NPN晶体管和一只PNP晶体管组成的调整管。
这种复合管的压降，VSAT (PNP)＋VBE (NPN) 通常大约为1V —比LDO高但比标准稳压器低。
图2 准LDO电路
LDO稳压器通常根据压差要求作最佳选择，通常压差在100 mV～200 mV 范围。
然而，LDO的缺点是其接地引脚的电流通常比准LDO或标准稳压器大。
标准稳压器比其它类型稳压器具有较大的压差，较大的功耗和较低的效率。
大多数情况下可使用LDO稳压器代替标准稳压器，但是应该考虑到LDO稳压器的最大输入电压指标比标准稳压器低。
此外，有些LDO需要精心挑选外部电容器以保持稳定性。
这三种类型稳压器在带宽和动态稳定性考虑因素方面也有些不同。
LDO结构
在图1中，调整管是PMOS晶体管。然而，稳压器可能使用各种类型的调整管，
因此可以根据所使用的调整管类型对LDO分类。
不同结构和特性的LDO具有不同的优点和缺点。
四种类型调整管示例如图3所示，
包括NPN双极型晶体管、PNP双极型晶体管、
复合晶体管和PMOS晶体管。
对于给定的电源电压，双极型调整管可提供最大的输出电流。
PNP优于NPN，因为PNP的基极可以与地连接，必要时使晶体管完全饱和。
NPN的基极只能与尽可能高的电源电压连接，从而使最小压降限制到一个VBE结压降。
因此，NPN管和复合调整管不能提供小于1V的压差。
然而它们在需要宽带宽和抗容性负载干扰时非常有用（因为它们具有低输出阻抗ZOUT特性）。
PMOS和PNP晶体管可以快速达到饱和，从而能使调整管电压损耗和功耗最小，从而允许用作低压差、低功耗稳压器。
PMOS调整管可以提供尽可能最低的电压降，大约等于RDS(ON)×IL。它允许达到最低的静态电流。
PMOS调整管的主要缺点是MOS 晶体管通常用作外部器件—
特别当控制大电流时—从而使IC构成一个控制器，而不能构成一个自身完整的稳压器。
一个完整稳压器的总功耗是 PD = (VIN – VOUT) IL + VINIGND
上面关系式的第一部分是调整管的功耗；
第二部分是电路控制器部分的功耗。
有些稳压器的接地电流，特别是那些用饱和双极型晶体管作调整管的稳压器，会在上电期间达到峰值。
低饱和型稳压压器（LDO）的方框图
随着便携式设备（电池供电）在过去十年间的快速增长，
象原来的业界标准 LM340 和 LM317 这样的稳压器件已经无法满足新的需要。
这些稳压器使用NPN 达林顿管，在本文中称其为NPN 稳压器（NPN regulators）。
预期更高性能的稳压器件已经由新型的
低压差（Low-dropout）稳压器（LDO）和
准LDO稳压器（quasi-LDO）实现了。
NPN 稳压器（NPN regulators）
在NPN稳压器（图1：NPN稳压器内部结构框图）的内部
使用一个 PNP管来驱动 NPN 达林顿管（NPN Darlington pass transistor），
输入输出之间存在至少1.5V～2.5V的压差（dropout voltage）。
这个压差为：Vdrop ＝ 2Vbe ＋Vsat（NPN 稳压器） （1）
LDO 稳压器（LDO regulators）
在LDO(Low Dropout)稳压器（图2：LDO稳压器内部结构框图）中，导通管是一个PNP管。
LDO的最大优势就是PNP管只会带来很小的导通压降，满载（Full-load）的跌落电压的典型值小于500mV，
轻载（Light loads）时的压降仅有10～20mV。LDO的压差为：
Vdrop ＝ Vsat （LDO 稳压器） （2）
准LDO 稳压器（Quasi-LDO regulators）
准LDO（Quasi-LDO）稳压器（图3： 准 LDO 稳压器内部结构框图）
已经广泛应用于某些场合，例如：5V到3.3V 转换器。
准LDO介于 NPN 稳压器和 LDO 稳压器之间而得名， 导通管是由单个PNP 管来驱动单个NPN 管。
因此，它的跌落压降介于NPN稳压器和LDO之间：Vdrop ＝ Vbe ＋Vsat （3）
稳压器的工作原理（Regulator Operation）
所有的稳压器，都利用了相同的技术实现输出电压的稳定（图4：稳压器工作原理图）。
输出电压通过连接到误差放大器（Error Amplifier）反相输入端（Inverting Input）
的分压电阻（Resistive Divider）采样（Sampled），
误差放大器的同相输入端（Non-inverting Input）连接到一个参考电压Vref。
参考电压由IC内部的带隙参考源(Bandgap Reference)产生。
误差放大器总是试图迫使其两端输入相等。
为此，它提供负载电流以保证输出电压稳定：
Vout = Vref(1 + R1 / R2) （4）
性能比较(Performance Comparison)
NPN，LDO和准LDO在电性能参数上的最大区别是：
跌落电压（Dropout Voltage）和地脚电流（Ground Pin Current）。
跌落电压前文已经论述。为了便于分析，我们定义地脚电流为Ignd （参见图4），并忽略了IC到地的小偏置电流。
那么，Ignd等于负载电流IL除以导通管的增益。
NPN 稳压器中，达林顿管的增益很高（High Gain）， 所以它只需很小的电流来驱动负载电流IL。
这样它的地脚电流Ignd也会很低，一般只有几个mA。
准LDO也有较好的性能，如国半（NS）的LM1085能够输出3A的电流却只有10mA的地脚电流。
然而，LDO的地脚电流会比较高。
在满载时，PNP管的β值一般是15～20。也就是说LDO的地脚电流一般达到负载电流的7%。
NPN稳压器的最大好处就是无条件的稳定，大多数器件不需额外的外部电容。
LDO在输出端最少需要一个外部电容以减少回路带宽（Loop Bandwidth）
及提供一些正相位转移（Positive Phase Shift）补偿。
准LDO一般也需要有输出电容，但容值要小于LDO的并且电容的ESR局限也要少些。
10.3串联、开关式稳压电路
10.3.1 线性串联稳压电路
1、线性串联型稳压电路的工作原理
稳压二极管的缺点是工作电流较小，稳定电压值不能连续调节。线性串联型稳压电源工作电流较大，
输出电压一般可连续调节，稳压性能优越。目前这种稳压电源已经制成单片集成电路，
广泛应用在各种电子仪器和电子电路之中。线性串联型稳压电源的缺点是损耗较大、效率低。
(1) 线性串联型稳压电源的构成
线性串联型稳压电源的工作原理可以用图10.19加以说明。
显然，VO =VI- VR，当VI增加时，R受控制而增加，使VR增加，从而在一定程度上抵消了VI增加对输出电压的影响。
若负载电流IL增加，R受控制而减小，使VR减小，从而在一定程度上抵消了因IL增加，使VI减小，对输出电压减小的影响。
在实际电路中，可变电阻R是用一个三极管来替代的，
控制基极电位，从而就控制了三极管的管压降VCE，VCE相当于VR。
要想输出电压稳定，必须按电压负反馈电路的模式来构成串联型稳压电路。
典型的串联型稳压电路如图10.20所示。
它由调整管、放大环节、比较环节、基准电压源几个部分组成。
1．输入电压变化，负载电流保持不变
输入电压VI的增加，必然会使输出电压VO有所增加，
输出电压经过取样电路取出一部分信号VF与基准源电压VREF比较，获得误差信号ΔV。
误差信号经放大后，用VO1去控制调整管的管压降VCE增加，从而抵消输入电压增加的影响。 
2．负载电流变化，输入电压保持不变
负载电流IL的增加，必然会使输入电压VI有所减小，输出电压VO必然有所下降，
经过取样电路取出一部分信号VF与基准电压源VREF比较，获得的误差信号使VO1增加，
从而使调整管的管压降VCE下降，从而抵消因IL增加使输入电压减小的影响。 
3．输出电压调节范围的计算 
调节R2显然可以改变输出电压。
一，来自百度的说明
LDO是low dropout regulator，意为低压差线性稳压器，是相对于传统的线性稳压器来说的。传统的线性稳压器，如78xx系列的芯片都要求输入电压要比输出电压高出2v~3V以上，否则就不能正常工作。但是在一些情况下，这样的条件显然是太苛刻了，如5v转3.3v,输入与输出的压差只有1.7v，显然是不满足条件的。针对这种情况，才有了LDO类的电源转换芯片。
二，什么是线性稳压器
线性稳压器主要包括普通线性稳压器和LDO（Low Dropout Regulator，低压差线性稳压器）两种类型，它们的主要区别是：普通线性稳压器（如常见的78系列三端稳压器）工作时要求输入与输出之间的压差值较大（一般要求在2～3V以上），功耗较高；而LDO工作时要求输入与输出之间的压差值较小（可以为IV以下甚至更低），功耗较低。
（1）线性稳压器基本工作原理
线性稳压器是通过输出电压反馈，经误差放大器等组成的控制电路来控制调整管的管压降VDD（即压差）来达到稳压的目的，其原理框图如图1所示。特点是VIN必须大于VOUT，调整管工作在线性区（线性稳压器从此得名）。输入电压的变动或负载电流的变化引起输出电压变动时，通过反馈及控制电路，改变VDO的大小，使输出电压VOUT基本不变。
普通线性稳压器和LD0的工作原理是一致的，不同的是，二者采用的调整管结构不同，从而使LD0比普通线性稳压器压差更小，功耗更低。
有些液晶显示器中使用的线性稳压器设有输出控制端，也就是说，这种稳压器输出电压受控制端的控制。图2所示是可控稳压器的内部框图。
三，LDO初步认识
LDO 是一种线性稳压器。线性稳压器使用在其线性区域内运行的晶体管或 FET，从应用的输入电压中减去超额的电压，产生经过调节的输出电压。所谓压降电压，是指稳压器将输出电压维持在其额定值上下 100mV 之内所需的输入电压与输出电压差额的最小值。
V压降=MIN（Vin-Vout）|Vout+100mv
正输出电压的LDO（低压降）稳压器通常使用功率晶体管（也称为传递设备）作为 PNP。这种晶体管允许饱和，所以稳压器可以有一个非常低的压降电压，通常为 200mV 左右；与之相比，使用 NPN 复合电源晶体管的传统线性稳压器的压降为 2V 左右。负输出 LDO 使用 NPN 作为它的传递设备，其运行模式与正输出 LDO 的 PNP设备类似。
更新的发展使用 MOS 功率晶体管，它能够提供最低的压降电压。使用功率MOS，通过稳压器的唯一电压压降是电源设备负载电流的 ON 电阻造成的。如果负载较小，这种方式产生的压降只有几十毫伏。
新的LDO线性稳压器可达到以下指标：输出噪声30μV，PSRR为60dB，静态电流6μA（TI的TPS78001达到Iq=0.5uA），电压降只有100mV(TI量产了号称0.1mV的LDO)。LDO线性稳压器的性能之所以能够达到这个水平，主要原因在于其中的调整管是用P沟道MOSFET，而普通的线性稳压器是使用PNP晶体管。P沟道MOSFET是电压驱动的，不需要电流，所以大大降低了器件本身消耗的电流；另一方面，采用PNP晶体管的电路中，为了防止PNP晶体管进入饱和状态而降低输出能力， 输入和输出之间的电压降不可以太低；而P沟道MOSFET上的电压降大致等于输出电流与导通电阻的乘积。由于MOSFET的导通电阻很小，因而它上面的电压降非常低。
如果输入电压和输出电压很接近，最好是选用LDO稳压器，可达到很高的效率。所以，在把锂离子电池电压转换为3V输出电压的应用中大多选用LDO稳压器。虽说电池的能量最後有百分之十是没有使用，LDO稳压器仍然能够保证电池的工作时间较长，同时噪音较低。
如果输入电压和输出电压不是很接近，就要考虑用开关型的DCDC了，因为从上面的原理可以知道，LDO的输入电流基本上是等于输出电流的，如果压降太大，耗在LDO上能量太大，效率不高。
DC-DC转换器包括升压、降压、升/降压和反相等电路。DC-DC转换器的优点是效率高、可以输出大电流、静态电流小。随着集成度的提高，许多新型DC-DC转换器仅需要几只外接电感器和滤波电容器。但是，这类电源控制器的输出脉动和开关噪音较大、成本相对较高。
总的来说，升压是一定要选DCDC的，降压，是选择DCDC还是LDO，要在成本，效率，噪声和性能上比较。
挑選線性穩壓器 (LDO)
固定輸出電壓的LDO具有內部回饋網路，輸出電壓可調的LDO要使用外部回饋網路，以此提供更大彈性。
一些輸出可調的元件同時也具有內部回饋網路，因此也可作為固定輸出版本使用。
- V IN(MIN) > 2.5V : PMOS類型的 LDO
- V IN(MIN)>1.0V : 使用外加偏置電壓或內置電荷泵升壓偏置的NMOS型 LDO
LDO design techniques for small spaces
A key challenge to the ultra-miniaturization of electronic systems is power management. As any electronics engineer knows, when overall system sizes shrink the amount of area available for energy storage and energy conversion shrinks with it. This is happening in many market-growing applications, such as implantable medical devices, Internet-of-things (IoT) electronics, and wearable electronics. While the size of the electronics continues to scale, the batteries and capacitors required to store energy are not keeping up. The consequence is that often times the area required for energy storage and power management dominates the overall form factor of the final product.
Due to these area limitations energy must be stored in an efficient form. Often times the most efficient form is at a higher potential and with significant noise components. A voltage regulator – such as an LDO – is then required to regulate this supply voltage down to the level at which the system operates.
A key figure of merit in low power LDO design is current efficiency. Current efficiency is defined as the ratio of Iload to Itotal. This ratio is the percentage of overall power drawn from the power supply that is delivered to the load. For high power applications it is common for this number to exceed 99 percent. However, this is very different in low power design. If, for example, the total load current is 10uA, every 1uA of quiescent current in the LDO results in a 10% drop in current efficiency. In an already power constrained system this loss in efficiency can be catastrophic. As such, design methods that minimize the overall LDO quiescent current are critical. A properly designed LDO will maintain overall system efficiency and long battery life, minimizing the need for large energy storage elements.
A Short LDO Design Overview
Figure 1 shows an LDO block diagram utilizing an NMOS pass transistor.
Consider applications where the unregulated power supply voltage (Vsply) is much greater than the regulated output voltage (Vreg).
Here, a simple NMOS pass transistor architecture is usually the best choice.
LDO block diagram with NMOS pass transistor.
This architecture has many desirable properties, two of which are trivial frequency compensation and a small FET area.
A small FET area is a result of the higher mobility of charge carriers in NMOS FETs (electrons) versus that of PMOS FETs (holes).
The ease of frequency compensation is due to the dominant pole being at the gate of the NMOS pass transistor instead of at the output node.
LDOs are typically two pole systems, with some architectures including a zero and / or an additional high frequency pole.
The NMOS LDO shown in figure 1 is a simple two pole system.
Therefore, stability is achieved by setting the frequency of pole P1 more than one decade below pole P2.
As long as the two poles, P1 and P2, are well separated this LDO will be closed-loop stable.
This is assuming that the error amplifier is a simple OTA with a single dominant pole at the output node.
Once the output capacitor size (Cout) is determined (set by high frequency load transient requirements, such as digital logic switching), pole P1 can be calculated.
P1 is set by the product of the error amplifiers output impedance (ro) and the compensation capacitor (Cc).
By increasing ro we are able to simultaneously achieve low P1 frequency and high loop gain, both very desirable traits.
It is important to remember that in an OTA design, high output impedance does not cost extra current just extra area.
This enables the OTA, and correspondingly the LDO, quiescent current to be the minimum value required for unity gain bandwidth.
This is an application specific requirement that sets the base line for quiescent current in a traditional LDO architecture.
In many applications a quiescent current of only 100nA to 200nA is sufficient.
This results in a current efficiency that is greater than 98 percent.
It is worth noting that slew-rate enhanced LDOs are capable of going below this minimum current, but at a significant cost in terms of size and complexity.
Therefore, in an NMOS LDO, both stability and low quiescent current go hand-in-hand.
But nothing comes for free. The NMOS LDO has one very large shortcoming.
The minimum supply voltage (or overhead voltage) is Vgs(MN) + Vsat(MN) + Vreg
which is approximately equal to 2Vsat(MN) + Vth + Vreg.
Even if a native threshold NMOS transistor is used (Vth = ∼0V) this is double the overhead voltage of using a PMOS pass transistor.
This is a major shortcoming that prevents the NMOS LDO from being used in many applications.
It is also worth noting that use of a native threshold NMOS pass transistor is typically not advised.
This is because across process corners these devices are very difficult to fully turn off, resulting in Vreg drifting up.
The alternative to an NMOS LDO architecture is a PMOS LDO.
The PMOS LDO has the distinct advantage over the NMOS LDO of true “low-dropout” operation.
This topology is capable of regulating the supply down to just one Vsat over the output voltage (<100mV is readily achievable).
This, however, comes at the cost of significantly more challenging design tradeoffs.
Many of these design tradeoffs are the consequence of pole position P1 and P2 swapping locations.
While on the surface this seems like a small difference, it actually has very large implications to error amplifier design and overall LDO quiescent current.
These implications and more will be covered in a future post to come soon.
