ARM architectures

https://gitorious.org/freebsd/freebsd/raw/56c5165837bf08f50ca4a08c6b2da91f73852960:sys/arm/include/acle-compat.h

/*
 * Copyright (c) 2014 ARM Ltd
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 * modification, are permitted provided that the following conditions
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 * 3. The name of the company may not be used to endorse or promote
 *    products derived from this software without specific prior written
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#ifndef __ARM_ARCH

/* ACLE standardises a set of pre-defines that describe the ARM architecture.
   These were mostly implemented in GCC around GCC-4.8; older versions
   have no, or only partial support.  To provide a level of backwards
   compatibility we try to work out what the definitions should be, given
   the older pre-defines that GCC did produce.  This isn't complete, but
   it should be enough for use by routines that depend on this header.  */

/* No need to handle ARMv8, GCC had ACLE support before that.  */

#define __ARM_ACLE 101

# ifdef __ARM_ARCH_7__
/* The common subset of ARMv7 in all profiles.  */
#  define __ARM_ARCH 7
#  define __ARM_ARCH_ISA_THUMB 2
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_LDREX 7
#  define __ARM_FEATURE_UNALIGNED
# endif

# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
#  define __ARM_ARCH 7
#  define __ARM_ARCH_ISA_THUMB 2
#  define __ARM_ARCH_ISA_ARM
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_SIMD32
#  define __ARM_FEATURE_DSP
#  define __ARM_FEATURE_QBIT
#  define __ARM_FEATURE_SAT
#  define __ARM_FEATURE_LDREX 15
#  define __ARM_FEATURE_UNALIGNED
#  ifdef __ARM_ARCH_7A__
#   define __ARM_ARCH_PROFILE 'A'
#  else
#   define __ARM_ARCH_PROFILE 'R'
#  endif
# endif

# ifdef __ARM_ARCH_7EM__
#  define __ARM_ARCH 7
#  define __ARM_ARCH_ISA_THUMB 2
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_SIMD32
#  define __ARM_FEATURE_DSP
#  define __ARM_FEATURE_QBIT
#  define __ARM_FEATURE_SAT
#  define __ARM_FEATURE_LDREX 7
#  define __ARM_FEATURE_UNALIGNED
#  define __ARM_ARCH_PROFILE 'M'
# endif

# ifdef __ARM_ARCH_7M__
#  define __ARM_ARCH 7
#  define __ARM_ARCH_ISA_THUMB 2
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_QBIT
#  define __ARM_FEATURE_SAT
#  define __ARM_FEATURE_LDREX 7
#  define __ARM_FEATURE_UNALIGNED
#  define __ARM_ARCH_PROFILE 'M'
# endif

# ifdef __ARM_ARCH_6T2__
#  define __ARM_ARCH 6
#  define __ARM_ARCH_ISA_THUMB 2
#  define __ARM_ARCH_ISA_ARM
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_SIMD32
#  define __ARM_FEATURE_DSP
#  define __ARM_FEATURE_QBIT
#  define __ARM_FEATURE_SAT
#  define __ARM_FEATURE_LDREX 4
#  define __ARM_FEATURE_UNALIGNED
# endif

# ifdef __ARM_ARCH_6M__
#  define __ARM_ARCH 6
#  define __ARM_ARCH_ISA_THUMB 1
#  define __ARM_ARCH_PROFILE 'M'
# endif

# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
  || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
  || defined (__ARM_ARCH_6ZK__)
#  define __ARM_ARCH 6
#  define __ARM_ARCH_ISA_THUMB 1
#  define __ARM_ARCH_ISA_ARM
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_SIMD32
#  define __ARM_FEATURE_DSP
#  define __ARM_FEATURE_QBIT
#  define __ARM_FEATURE_SAT
#  define __ARM_FEATURE_UNALIGNED
#  ifndef __thumb__
#   if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
#    define __ARM_FEATURE_LDREX 15
#   else
#    define __ARM_FEATURE_LDREX 4
#   endif
#  endif
# endif

# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
#  define __ARM_ARCH 5
#  define __ARM_ARCH_ISA_ARM
#  ifdef __ARM_ARCH_5TE__
#   define __ARM_ARCH_ISA_THUMB 1
#  endif
#  define __ARM_FEATURE_CLZ
#  define __ARM_FEATURE_DSP
# endif

# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
#  define __ARM_ARCH 5
#  define __ARM_ARCH_ISA_ARM
#  ifdef __ARM_ARCH_5TE__
#   define __ARM_ARCH_ISA_THUMB 1
#  endif
#  define __ARM_FEATURE_CLZ
# endif

# ifdef __ARM_ARCH_4T__
#  define __ARM_ARCH 4
#  define __ARM_ARCH_ISA_ARM
#  define __ARM_ARCH_ISA_THUMB 1
# endif

# ifdef __ARM_ARCH_4__
#  define __ARM_ARCH 4
#  define __ARM_ARCH_ISA_ARM
# endif

# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
#  define __ARM_ARCH 3
#  define __ARM_ARCH_ISA_ARM
# endif

# ifdef __ARM_ARCH_2__
#  define __ARM_ARCH 2
#  define __ARM_ARCH_ISA_ARM
# endif

# ifdef __ARMEB__
#  define __ARM_BIG_ENDIAN
# endif

/* If we still don't know what the target architecture is, then we're
   probably not using GCC.  */
# ifndef __ARM_ARCH
#  error Unable to determine architecture version.
# endif

#endif /* __ARM_ARCH  */

http://en.wikipedia.org/wiki/ARM_architecture

Architecture	Bit width	Cores designed by ARM Holdings	Cores designed by third parties	Cortex profile	References
ARMv1	32/26	ARM1
ARMv2	32/26	ARM2, ARM3	Amber, STORM Open Soft Core^[28]
ARMv3	32	ARM6, ARM7
ARMv4	32	ARM8	StrongARM, FA526
ARMv4T	32	ARM7TDMI, ARM9TDMI
ARMv5	32	ARM7EJ, ARM9E, ARM10E	XScale, FA626TE, Feroceon, PJ1/Mohawk
ARMv6	32	ARM11
ARMv6-M	32	ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1		Microcontroller
ARMv7-M	32	ARM Cortex-M3		Microcontroller
ARMv7E-M	32	ARM Cortex-M4		Microcontroller
ARMv7-R	32	ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7		Real-time
ARMv7-A	32	ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17	Krait, Scorpion, PJ4/Sheeva, Apple A6/A6X (Swift)	Application
ARMv8-A	64/32	ARM Cortex-A53, ARM Cortex-A57^[29]	X-Gene, Denver, Apple A7 (Cyclone), AMD K12	Application	^[30]^[31]
ARMv8-R	32	No announcements yet		Real-time	^[32]^[33]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is provided by ARM Holdings.^[34]

Designed by ARM[edit]

ARM family	ARM architecture	ARM core	Feature	Cache (I / D),MMU	Typical MIPS @MHz
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	4 MIPS @ 8 MHz 0.33 DMIPS/MHz
ARM2	ARMv2a	ARM250	Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions	None, MEMC1a	7 MIPS @ 12 MHz
ARM3	ARMv2a	ARM3	First integrated memory cache	4 KB unified	12 MIPS @ 25 MHz 0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit)	None	10 MIPS @ 12 MHz
		ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)	4 KB unified	28 MIPS @ 33 MHz
		ARM610	As ARM60, cache, no coprocessor bus	4 KB unified	17 MIPS @ 20 MHz 0.65 DMIPS/MHz
ARM7	ARMv3	ARM700		8 KB unified	40 MHz
		ARM710	As ARM700, no coprocessor bus	8 KB unified	40 MHz
		ARM710a	As ARM710	8 KB unified	40 MHz 0.68 DMIPS/MHz
ARM7TDMI	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM26-bit addressing	None	15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz
		ARM710T	As ARM7TDMI, cache	8 KB unified, MMU	36 MIPS @ 40 MHz
		ARM720T	As ARM7TDMI, cache	8 KB unified, MMU with FCSE (Fast Context Switch Extension)	60 MIPS @ 59.8 MHz
		ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions	None
ARM8	ARMv4	ARM810^[4]^[5]	5-stage pipeline, static branch prediction, double-bandwidth memory	8 KB unified, MMU	84 MIPS @ 72 MHz 1.16 DMIPS/MHz
ARM9TDMI	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	None
		ARM920T	As ARM9TDMI, cache	16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)^[6]	200 MIPS @ 180 MHz
		ARM922T	As ARM9TDMI, caches	8 KB / 8 KB, MMU
		ARM940T	As ARM9TDMI, caches	4 KB / 4 KB, MPU
ARM9E	ARMv5TE	ARM946E-S	Thumb, Enhanced DSP instructions, caches	Variable, tightly coupled memories, MPU
		ARM966E-S	Thumb, Enhanced DSP instructions	No cache, TCMs
		ARM968E-S	As ARM966E-S	No cache, TCMs
	ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions	Variable, TCMs, MMU	220 MIPS @ 200 MHz
	ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	No caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)	32 KB / 32 KB, MMU
	ARMv5TE	ARM1022E	As ARM1020E	16 KB / 16 KB, MMU
	ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP)	Variable, MMU or MPU
ARM11	ARMv6	ARM1136J(F)-S^[7]	8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions	Variable, MMU	740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
	ARMv6T2	ARM1156T2(F)-S	8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions	Variable, MPU
	ARMv6Z	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	Variable, MMU + TrustZone	965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors^[8]
	ARMv6K	ARM11 MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	Variable, MMU
SecurCore	ARMv6-M	SC000			0.9 DMIPS/MHz
	ARMv4T	SC100
	ARMv7-M	SC300			1.25 DMIPS/MHz
Cortex-M	ARMv6-M	Cortex-M0^[9]	Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),^[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, no MPU	0.84 DMIPS/MHz
		Cortex-M0+^[11]	Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),^[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	0.93 DMIPS/MHz
		Cortex-M1^[12]	Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),^[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory	Optional cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, no MPU	136 DMIPS @ 170 MHz,^[13](0.8 DMIPS/MHz FPGA-dependent)^[14]
	ARMv7-M	Cortex-M3^[15]	Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz
	ARMv7E-M	Cortex-M4^[16]	Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz
Cortex-R	ARMv7-R	Cortex-R4^[17]	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstepwith fault logic	0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 8/12 regions
		Cortex-R5 (MPCore)^[18]	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)^[19]	0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 12/16 regions
		Cortex-R7 (MPCore)^[20]	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP^[19]	0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt MPU with 16 regions
Cortex-A	ARMv7-A	Cortex-A5^[21]	Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	4-64 KB / 4-64 KB L1, MMU + TrustZone	1.57 DMIPS/MHz per core
		Cortex-A7 MPCore^[22]	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design^[23]	32 KB / 32 KB L1, 0–4 MB L2, MMU + TrustZone	1.9 DMIPS/MHz per core
		Cortex-A8^[24]	Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalarpipeline	16-32 KB / 16–32 KB L1, 0–1 MB L2 opt ECC, MMU + TrustZone	Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
		Cortex-A9 MPCore^[25]	Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	16–64 KB / 16–64 KB L1, 0–8 MB L2 opt parity, MMU + TrustZone	2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC40G (dual-core)
		Cortex-A12^[26]	Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	32-64 KB / 32 KB L1, 256 KB-8 MB L2	3.0 DMIPS/MHz per core
		Cortex-A15 MPCore^[27]	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline^[23]	32 KB w/parity / 32 KB w/ECCL1, 0–4 MB L2, L2 has ECC, MMU + TrustZone	At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)^[28]
		Cortex-A17 MPCore	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP	MMU + TrustZone
Cortex-A50	ARMv8-A	Cortex-A53^[29]	Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline	8-64 KB w/parity / 8-64 KB w/ECC L1 per core, 128 KB-2 MB L2 shared, 40-bit physical addresses	2.3 DMIPS/MHz
Cortex-A50	ARMv8-A	Cortex-A57^[30]	Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline	48 KB w/DED parity / 32 KB w/ECC L1 per core, 512 KB-2 MB L2 shared, 44-bit physical addresses	At least 4.1 DMIPS/MHz per core (up to 4.76 DMIPS/MHz depending on implementation)
ARM family	ARM architecture	ARM core	Feature	Cache (I / D),MMU	Typical MIPS @ MHz

Designed by third parties[edit]

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Family	Instruction set	Microarchitecture	Feature	Cache (I / D), MMU	Typical MIPS @ MHz
StrongARM	ARMv4	SA-110	5-stage pipeline	16 KB / 16 KB, MMU	100–206 MHz 1.0 DMIPS/MHz
StrongARM	ARMv4	SA-1100	derivative of the SA-110	16 KB / 8 KB, MMU
Faraday^[31]	ARMv4	FA510	6-stage pipeline	Up to 32 KB / 32 KB cache, MPU	1.26 DMIPS/MHz 100–200 MHz
		FA526	6-stage pipeline	Up to 32 KB / 32 KB cache, MMU	1.26 MIPS/MHz 166-300 MHz
		FA626	8-stage pipeline	32 KB / 32 KB cache, MMU	1.35 DMIPS/MHz 500 MHz
	ARMv5TE	FA606TE	5-stage pipeline	No cache, no MMU	1.22 DMIPS/MHz 200 MHz
		FA626TE	8-stage pipeline	32 KB / 32 KB cache, MMU	1.43 MIPS/MHz 800 MHz
		FMP626TE	8-stage pipeline, SMP		1.43 MIPS/MHz 500 MHz
		FA726TE	13 stage pipeline, dual issue		2.4 DMIPS/MHz 1000 MHz
XScale	ARMv5TE	XScale	7-stage pipeline, Thumb, Enhanced DSP instructions	32 KB / 32 KB, MMU	133–400 MHz
		Bulverde	Wireless MMX, Wireless SpeedStep added	32 KB / 32 KB, MMU	312–624 MHz
		Monahans^[32]	Wireless MMX2 added	32 KB / 32 KB (L1), optional L2 cache up to 512 KB, MMU	Up to 1.25 GHz
MarvellSheeva	ARMv5	Feroceon	5-8 stage pipeline, single-issue	16 KB / 16 KB, MMU	600–2000 MHz
		Jolteon	5-8 stage pipeline, dual-issue	32 KB / 32 KB, MMU	600–2000 MHz
		PJ1 (Mohawk)	5-8 stage pipeline, single-issue, Wireless MMX2	32 KB / 32 KB, MMU	1.46 DMIPS/MHz 1.06 GHz
	ARMv6 / ARMv7-A	PJ4	6-9 stage pipeline, dual-issue, Wireless MMX2, SMP	32 KB / 32 KB, MMU	2.41 DMIPS/MHz 1.6 GHz
Snapdragon	ARMv7-A	Scorpion^[33]	1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)	256 KB L2 per core	2.1 DMIPS/MHz per core
Snapdragon	ARMv7-A	Krait^[33]	1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)	4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core	3.3 DMIPS/MHz per core
Apple A6, Apple A6X	ARMv7-A	Swift^[34]	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON	L1: 32 KB / 32 KB, L2: 1 MB	3.5 DMIPS/MHz per core
Apple A7	ARMv8-A	Cyclone	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone /AArch64	L1: 64 KB / 64 KB, L2: 1 MB	1.3 GHz
Apple A8	ARMv8-A	Cyclone gen 2	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone /AArch64	L1: (unknown);KB, L2: (unknown);MB	1.4 GHz
X-Gene	ARMv8-A	X-Gene	64-bit, quad issue, SMP, 64 cores^[35]	Cache, MMU, virtualization	3 GHz
Denver	ARMv8-A	Denver	64-bit	128 KB I / 64 KB D	Up to 2.5 GHz
ThunderX	ARMv8-A	ThunderX	8-16 / 24-48 cores (×2 w/two chips). 64-bit		Up to 2.5 GHz

ARM core timeline[edit]

The following table lists each core by the year it was announced.^[36]^[37]

Year	Classic cores					Cortex cores
Year	ARM7	ARM8	ARM 9	ARM10	ARM11	Embedded	Real-time	Application
1996		ARM810
1997			ARM9TDMI
1998	ARM7TDMI(-S)
1999
2000
2001
2002					ARM1136J(F)-S
2003			ARM966E-S ARM968E-S		ARM1156T2(F)-S ARM1176JZ(F)-S
2004						Cortex-M3
2005								Cortex-A8
2006			ARM996HS
2007						Cortex-M1		Cortex-A9
2008
2009						Cortex-M0		Cortex-A5
2010						Cortex-M4		Cortex-A15
2011							Cortex-R4 Cortex-R5 Cortex-R7	Cortex-A7
2012						Cortex-M0+		Cortex-A53 Cortex-A57
2013								Cortex-A12
2014								Cortex-A17

posted @ 2014-09-13 00:32 IAmAProgrammer 阅读(1187) 评论(0) 编辑收藏举报

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