1 -------------------------------------------------------------------------------
2 -- Filename: fifo.vhd
3 --
4 -- Description:
5 -- A small-to-medium depth FIFO.
6 -- For data storage, the SRL elements native to the target FGPA family are used.
7 -- If the FIFO depth exceeds the available depth of the SRL elements,
8 -- then SRLs are cascaded and MUXFN elements are used
9 -- to select the output of the appropriate SRL stage.
10 --
11 -- Features:
12 --
13 -- Width and depth are arbitrary, but each doubling of depth,
14 -- starting from the native SRL depth, adds a level of MUXFN.
15 -- Generally, in performance-oriented applications,
16 -- the fifo depth may need to be limited to not exceed the SRL cascade depth
17 -- supported by local fast interconnect or the number of MUXFN levels.
18 --
19 -- However, deeper fifos will correctly build.
20 --
21 -- Commands: read, write.
22 -- Flags: empty and full.
23 --
24 --
25 -- The Addr output is always one less than the current occupancy
26 -- when the FIFO is non-empty, and is all ones when FIFO is empty.
27 -- Therefore, the value <FIFO_Empty, Addr> as a signed value,
28 -- is one less than the current occupancy.
29 --
30 -- <'1', "1111" > => -1 + 1 => 0 : FIFO is empty.
31 --
32 -- <'0', "0000" > => 0 + 1 => 1 : FIFO has 1 data
33 -- <'0', "1111" > => 15 + 1 => 16 : FIFO has 16 data
34 --
35 -- <'0', "0000" > => 0 + 1 => 1 : FIFO has 1 data
36 -- <'1', "1111" > => -1 + 1 => 0 : FIFO is empty.
37 --
38 -- This information can be used to generate additional flags, if needed.
39 --
40 ----------------------------------------------------------------------------------
41 library IEEE;
42 use IEEE.STD_LOGIC_1164.all;
43
44 -- Uncomment the following library declaration if using
45 -- arithmetic functions with Signed or Unsigned values
46 use IEEE.NUMERIC_STD.all;
47
48 -- Uncomment the following library declaration if instantiating
49 -- any Xilinx primitives in this code.
50 --library UNISIM;
51 --use UNISIM.VComponents.all;
52 use work.my_func_pack.all;
53 use work.my_comp_pack.all;
54
55 entity fifo is
56 generic (
57 C_DWIDTH : natural := 8;
58 C_DEPTH : positive := 16 );
59 port (
60 Clk : in std_logic;
61 Reset : in std_logic;
62 FIFO_Write : in std_logic;
63 Data_In : in std_logic_vector(0 to C_DWIDTH-1);
64 FIFO_Read : in std_logic;
65 Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
66 FIFO_Full : out std_logic;
67 FIFO_Empty : out std_logic;
68 Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
69 );
70 end fifo;
71
72 architecture Behavioral of fifo is
73
74 constant ADDR_BITS : integer := clog2(C_DEPTH);
75 constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
76
77 begin
78
79 fifo_i : fifo_rbu
80 generic map (
81 C_DWIDTH => C_DWIDTH,
82 C_DEPTH => C_DEPTH)
83 port map (
84 Clk => Clk,
85 Reset => Reset,
86 FIFO_Write => FIFO_Write,
87 Data_In => Data_In,
88 FIFO_Read => FIFO_Read,
89 Data_Out => Data_Out,
90 FIFO_Full => FIFO_Full,
91 FIFO_Empty => FIFO_Empty,
92 Addr => Addr,
93 Num_To_Reread => ZEROES,
94 Underflow => open,
95 Overflow => open
96 );
97
98 end Behavioral;
