Count to Value, vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package pack is
 function CountToValue( Count: unsigned; ConstValue : natural)
 return boolean;
end pack;

package body pack is
 function CountToValue( Count: unsigned; ConstValue : natural)
 return boolean is
 variable ret : boolean;
 variable AndResult : std_logic;
 variable UnsingedConstValue : unsigned ( Count'range);
 begin
 ret := FALSE;
 AndResult := '1';
 UnsingedConstValue := to_unsigned( ConstValue, UnsingedConstValue'length);
 for I in Unsigned'range loop
 if UnsingedConstValue(I) = '1' then
 AndResult := AndResult and Count(I);
 end if;
 end loop;

if AndResult = '1' then
 ret := TRUE;
 end if;

return ret;
 end UnsignedIsValue;
end pack;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

use work.pack.all;
entity xxxx is
 Port ( x : in unsigned( 15 downto 0 );
 y : in unsigned( 15 downto 0 );
 a : in unsigned( 15 downto 0 );
 w : out STD_LOGIC;
 z : out STD_LOGIC);
end xxxx;

architecture Behavioral of xxxx is

begin
 z <= '1' when x=to_unsigned(125, x'length) and y=to_unsigned(17, y'length) and a=to_unsigned(16, y'length) else '0';
 w <= '1' when UnsignedIsValue(x,125) and UnsignedIsValue(y, 17) and UnsignedIsValue(a, 16) else '0';

end Behavioral;