随笔分类 - XILINX
摘要：XAPP906Supporting Multiple SD Devices with CoolRunner-II CPLDsThere has been an increasing demand to add multiple Secure Digital (SD) devices in a sin...
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摘要：http://forums.xilinx.com/t5/Configuration/Spartan6-slave-SelectMap-configuration-fails-owing-to-JTAG/td-p/504815I have a board with a XC6SLX9 which is...
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摘要：http://www.121down.com/article/article_13651.html坑爹的ISE对win8无法完美支持（包括目前最新的14.6），在使用64位ISE时点击OPEN之类的东西时程序都会崩溃，虽然使用32位不会有这个问题，但是工程的默认打开方式不能改为32位。因此想要正常（...
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摘要：http://thehardwarer.com/2013/05/minispartan-6-another-spartan-6-kit/miniSpartan6 is an Opens Source FPGA starter kit that I designed and built based on other open source kits such as Papilio Proand XuLA2.It is designed around Spartan 6 chip fromXilinxand it has on board JTAG programmer based onFT223
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摘要：http://www.xess.com/prods/prod048.phpXuLAhttp://www.xess.com/prods/prod055.phpXuLA2http://www.xess.com/manuals/XuLA-manual.pdfFPGAThe programmable logic device on the XuLA Board is either a XILINX 200,000-gate XC3S200A Spartan 3A FPGA in a 100-pin VQFP, or a 50,000-gate XC3S50A.MicrocontrollerThe Xu
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摘要：http://papilio.cc/index.php?n=Papilio.PapilioOneThe Papilio is an Open Source FPGA development board based on the Xilinx Spartan 3E FPGA (datasheet). It has 48 I/O lines, dual channel USB, integrated JTAG programmer, 4 power supplies, and a power connector. It provides everything needed to start lea
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摘要：http://forums.xilinx.com/t5/General-Technical-Discussion/Configuring-spartan-6-using-mcu-and-spi-flash/td-p/88658I'm currently using spartan 6 in my design and I was wondering if I could configure it using MCU to download fpga design file into the spi flash. In other word, can I download a prom
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摘要：These configuration pins serve as the interfacefor a number of different configuration modes:• JTAG configuration mode• Master Serial/SPI configuration mode (x1, x2, and x4)• Slave Serial configuration mode• Master SelectMAP/BPI configuration mode (x8 and x16)• Slave SelectMAP configuration mode (x8
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摘要：http://www.xilinx.com/support/answers/35171.htmHow to connect the following pins in my design?CMPMISOCMPMOSICMPCLKCMPCS_BCMPMISO - Reserved for future use. Use these pins as general-purpose I/O.CMPMOSI - Reserved for future use. Use these pins as general-purpose I/O.CMPCLK - Reserved for future use.
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摘要：The SILICA Xynergy-M4 Board combines an ARM Cortex-M4 based STMicroelectronics STM32F417 controller with a Xilinx Spartan-6 low-cost FPGA (XC6SLX16) in one design.There are numerous development tools for either ARM Cortex-M microcontrollers or FPGA kits, but this is the first module in the market th
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摘要：Key FeaturesHigh-performance FPGA configuration and PROM/CPLD programmingIncludes innovative FPGA-based acceleration firmware encapsulated in a small form factor pod attached to the cableSupports JTAG and Slave-Serial programming topologiesFirmware downloadable over cableEasy to useFully integrated
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摘要：http://debugmo.de/2012/02/xvcd-the-xilinx-virtual-cable-daemon/I recently discovered an almost undocumented function in Xilinx ISE: the Xilinx virtual cable driver. It’s basically “a platform cable without a platform cable” (asmarcansaid so nicely) – it allows you use Impact (and Chipscope, and all
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