随笔分类 - FPGA
摘要：-- https://fpga4u.epfl.ch/wiki/FPGA4U_Description-- The SDRAM is an ISSI IS42S32800B. With 32 bits data bus, validated by SDRAM_DQM signals, -- one fo...
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摘要：Using a Virtex Device to Drive 5V CMOS-Level SignalsVoltage Level-Shifter Output Waveform
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摘要：XAPP906Supporting Multiple SD Devices with CoolRunner-II CPLDsThere has been an increasing demand to add multiple Secure Digital (SD) devices in a sin...
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摘要：Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO ...
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摘要：Must tri-state outputs and use an external resistor to pull up to 5VTo drive 5V CMOS-level inputs, a pull-up resistor must be applied to the 5V Virtex...
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摘要：When we engineers look at the complexity of system design these days, we are challenged with cramming more functions into a smaller space, while consu...
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摘要：http://davidkessner.wordpress.com/2011/05/01/adc-in-an-fpga/Geek Alert! What follows is very technical. It involves ADC’s, FPGA’s, and sophisticated e...
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摘要：http://www.design-reuse.com/articles/14886/fully-digital-implemented-delta-sigma-analog-to-digital-converter.htmlby Dr. MichaelGude &GerrietMuellerCol...
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摘要：http://www.eetimes.com/author.asp?section_id=36&doc_id=1320289Seeing the new ADC IP being bandied about by FPGA vendors got William Murray wondering w...
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摘要：http://www.21ic.com/app/eda/200905/42832.htmhttp://www.eefocus.com/article/09-10/84673s.html摘 要 简要分析sigma—deIta(∑一△)架构模数转换器(ADC)原理，提出一种基于FPGA内部LVDS(Lo...
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摘要：http://forums.xilinx.com/t5/General-Technical-Discussion/Configuring-spartan-6-using-mcu-and-spi-flash/td-p/88658I'm currently using spartan 6 in my design and I was wondering if I could configure it using MCU to download fpga design file into the spi flash. In other word, can I download a prom
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摘要：These configuration pins serve as the interfacefor a number of different configuration modes:• JTAG configuration mode• Master Serial/SPI configuration mode (x1, x2, and x4)• Slave Serial configuration mode• Master SelectMAP/BPI configuration mode (x8 and x16)• Slave SelectMAP configuration mode (x8
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摘要：http://www.altera.com/literature/hb/max2/max2_mii51009.pdfThe open-drain pin never drives high, only low or tri-state. When the open-drain pinis active, it drives low. When the open-drain pin is inactive, the pin is tri-stated and the trace pulls up to 5.0 V by the external resistor. The purpose of
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摘要：Connect a ARM Microcontroller to a FPGA using its Extended Memory Interface (EMI)http://elinux.org/Connect_a_ARM_Microcontroller_to_a_FPGA_using_its_Extended_Memory_Interface_(EMI)http://www.makestuff.eu/wordpress/software/fpgalink/http://www.techonlineindia.com/techonline/design_centers/170438/inte
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摘要：The SILICA Xynergy-M4 Board combines an ARM Cortex-M4 based STMicroelectronics STM32F417 controller with a Xilinx Spartan-6 low-cost FPGA (XC6SLX16) in one design.There are numerous development tools for either ARM Cortex-M microcontrollers or FPGA kits, but this is the first module in the market th
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摘要：http://www.silica.com/designers-community/forum/view/topic/fsmc_in_synchrnous_mode.htmlwith FSMC_CLK = 2 HCLK cycles, throughput for write is about 32MBytes/s.# STM32F2 runs at 120 MHz# FSMC CLK = 60 MHz#NET "FSMC_CLK" TNM_NET = FSMC_CLK;TIMESPEC TS_FSMC_CLK = PERIOD "FSMC_CLK" 6
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