ARM Cortex-M 分支指令编码

B<cond>.<qualifier> <lable> -- Branch causes a branch to a target address

if ConditionPassed(cond) then
{

  EncodingSpecificOperations(PC, lable);

  BranchWritePC(PC + imm32);

}

// All versions of the Thumb instruction set

T1 : B<cond> <lable> : not allowed in IT block

T2 : B<cond> <lable> : outside or last in IT block

// All versions of the Thumb instruction set from Thumb-2 onwards.

T3 : B<cond>.W <lable> : not allowed in IT block

T4 : B<cond>.W <lable> : outside or last in IT block

<lable>

Specifies the label of the instruction that is to be branched to.

The assembler calculates the required value of the offset
from the PC value of the B instruction to this label,
then selects an encoding that will set imm32 to that offset.

Allowed offsets are even numbers in the range

T1 : -256 to 254 : imm8

T2 : -2048 to 2046 : imm11

T3 : -1048576 to 1048574 : imm6 +  imm11 

T4 : -16777216 to 16777214 : imm10 +  imm11 

BX  -- Branch and Exchange causes a branch to an address and instruction set specified by a register.

T1 : BX<cond> <Rm> // Outside or last in IT block

BLX (register) -- Branch and Exchange calls a subroutine at an address and instruction set specified by a register.

T1 : BLX<cond> <Rm> // Outside or last in IT block

BL, BLX (immediate) -- Branch with Link (immediate) calls a subroutine at a PC-relative address.

T1 : BL<cond> <label> // Outside or last in IT block

T2 : BLX<cond> <label> // Outside or last in IT block