ARM Cortex-M 条件码 分支指令
Mnemonic Brief description See B Branch B, BL, BX, and BLX BL Branch with Link B, BL, BX, and BLX BLX Branch indirect with Link B, BL, BX, and BLX BX Branch indirect B, BL, BX, and BLX CBNZ Compare and Branch if Non Zero CBZ and CBNZ CBZ Compare and Branch if Zero CBZ and CBNZ IT If-Then IT TBB Table Branch Byte TBB and TBH TBH Table Branch Halfword TBB and TBH
Instruction Branch range B label -16 MB to +16 MB Is a branch (immediate). Bcond label (outside IT block) -1 MB to +1 MB Bcond label (inside IT block) -16 MB to +16 MB BL{cond} label -16 MB to +16 MB Is a branch with link (immediate). BX{cond} Rm Any value in register Is a branch indirect (register). BLX{cond} Rm Any value in register Is a branch indirect with link (register).
cond Is an optional condition code, see Conditional execution. label Is a PC-relative expression. See PC?relative expressions. Rm Is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0.
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block.
All other branch instructions can only be conditional inside an IT block, and are always unconditional otherwise, see IT.
when any of these instructions is inside an IT block, it must be the last instruction of the IT block.
Bcond is the only conditional instruction that is not required to be inside an IT block.
However, it has a longer branch range when it is inside an IT block.
You might have to use the .W suffix to get the maximum branch range.
Conditional execution
Most data processing instructions can optionally update the condition flags
in the Application Program Status Register (APSR) according to the result of the operation,
see Application Program Status Register.
Some instructions update all flags, and some only update a subset.
If a flag is not updated, the original value is preserved.
See the instruction descriptions for the flags they affect.
You can execute an instruction conditionally,
based on the condition flags set in another instruction, either:
immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or
by adding condition code suffixes to instructions.
See Table 3.4 for a list of the suffixes to add to instructions to make them conditional instructions.
The condition code suffix enables the processor to test a condition based on the flags.
If the condition test of a conditional instruction fails, the instruction:
does not execute
does not write any value to its destination register
does not affect any of the flags
does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block.
See IT for more information and restrictions when using the IT instruction.
Depending on the vendor, the assembler might automatically insert an IT instruction
if you have conditional instructions outside the IT block.
Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result.
The condition flags
The APSR contains the following condition flags:
31 30 29 28 27 26 --------------------- 0 N Z C V Q Reserved -------- Reserved [31] N Negative flag < bit31 of the result of the operation > [30] Z Zero flag < 1 if 0 == bit31..bit0 of the result of the operation > [29] C Carry or borrow flag [28] V Overflow flag [27] Q Saturation flag [26:0] - Reserved
N Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
C : A carry occurs:
if the result of an addition is greater than or equal to 2^32
if the result of a subtraction is positive or zero (>, >= )
as the result of an inline barrel shifter operation in a move or logical instruction.
( C <-- Bit[31] <-- ... <-- Bit[0] <-- 0 ) : LSL 1 ( C <-- Bit[31] <-- ... <-- Bit[0] <-- 0 ) : ASL 1 ( C <-- Bit[31] <-- ... <-- Bit[0] <-- Bit[31] ) : ROL 1 ( Bit[31] --> Bit[31] --> ... --> Bit[0] --> C ) : ASR 1 ( 0 --> Bit[31] --> ... --> Bit[0] --> C ) : LSR 1 ( Bit[0] --> Bit[31] --> ... --> Bit[0] --> C ) : ROR 1 ( C --> Bit[31] --> ... --> Bit[0] --> C ) : RRX RRX 可提供经右移一位后的寄存器中的值。 原先的进位标记将会移入位 [31]。 如果有 S 后缀，则将原先的位 [0] 存入进位标记中。 如果移位数为 0，则不会影响 C 标记。否则，C 标记会更新为移出的最后一位。
V : Overflow occurs when the sign of the result, in bit[31],
does not match the sign of the result had the operation been performed at infinite precision, for example:
if adding two negative values results in a positive value ( +a + +b = -c )
if adding two positive values results in a negative value ( -a + -b = +c )
if subtracting a positive value from a negative value generates a positive value ( -a - +b = +c )
if subtracting a negative value from a positive value generates a negative value.( +a - -b = -c )
Most instructions update the status flags only if the S suffix is specified.
Condition code suffixes
The instructions that can be conditional have an optional condition code,
shown in syntax descriptions as {cond}.
Conditional execution requires a preceding IT instruction.
An instruction with a condition code is only executed
if the condition code flags in the APSR meet the specified condition.
You can use conditional execution with the IT instruction
to reduce the number of branch instructions in code.
Application Program Status Register
Table 3.4 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Suffix Flags Meaning AL Can have any value Always. This is the default when no suffix is specified. ------------------------------------------------------------------------------------------------ MI N = 1 Negative bit[31] of the result PL N = 0 Positive or zero bit[31] of the result ------------------------------------------------------------------------------------------------ VS V = 1 Overflow VC V = 0 No overflow ------------------------------------------------------------------------------------------------ EQ Z = 1 Equal, unsigned or signed == NE Z = 0 Not equal, unsigned or signed != ------------------------------------------------------------------------------------------------ CC or LO C = 0 Lower, unsigned < LS C = 0 or Z = 1 Lower or same, unsigned <= CS or HS C = 1 Higher or same, unsigned >= HI C = 1 and Z = 0 Higher, unsigned > ------------------------------------------------------------------------------------------------ LT N != V Less than, signed < LE N != V and Z = 1 Less than or equal, signed <= GE N = V Greater than or equal, signed >= GT N = V and Z = 0 Greater than, signed >
