How can I discribe a ROM in VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is

  port
  (
    addr : in natural range 0 to 255;
    clk  : in std_logic;
    q    : out std_logic_vector(7 downto 0)
  );

end entity;

architecture rtl of single_port_rom is

  -- Build a 2-D array type for the RoM
  subtype word_t is std_logic_vector(7 downto 0);
  type memory_t is array(255 downto 0) of word_t;

  function init_rom
    return memory_t is
    variable tmp : memory_t := (others => (others => '0'));
  begin
    for addr_pos in 0 to 255 loop
        -- Initialize each address with the address itself
      tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, 8));
    end loop;
    return tmp;
  end init_rom;

  -- Declare the ROM signal and specify a default value.  Quartus II
  -- will create a memory initialization file (.mif) based on the 
  -- default value.
  signal rom : memory_t := init_rom;

begin

library ieee;
use ieee.std_logic_1164.all;

entity ROM is
  port ( address : in std_logic_vector(3 downto 0);
         data : out std_logic_vector(7 downto 0) );
end entity ROM;

architecture behavioral of ROM is
  type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
  constant my_Rom : mem := (
    0  => "00000000",
    1  => "00000001",
    2  => "00000010",
    3  => "00000011",
    4  => "00000100",
    5  => "11110000",
    6  => "11110000",
    7  => "11110000",
    8  => "11110000",
    9  => "11110000",
    10 => "11110000",
    11 => "11110000",
    12 => "11110000",
    13 => "11110000",
    14 => "11110000",
    15 => "11110000");
begin
   process (address)
   begin
     case address is
       when "0000" => data <= my_rom(0);
       when "0001" => data <= my_rom(1);
       when "0010" => data <= my_rom(2);
       when "0011" => data <= my_rom(3);
       when "0100" => data <= my_rom(4);
       when "0101" => data <= my_rom(5);
       when "0110" => data <= my_rom(6);
       when "0111" => data <= my_rom(7);
       when "1000" => data <= my_rom(8);
       when "1001" => data <= my_rom(9);
       when "1010" => data <= my_rom(10);

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is

  generic
  (
    DATA_WIDTH : natural := 8;
    ADDR_WIDTH : natural := 8
  );

  port
  (
    clk  : in std_logic;
    addr : in natural range 0 to 2**ADDR_WIDTH - 1;
    q    : out std_logic_vector((DATA_WIDTH -1) downto 0)
  );

end entity;

architecture rtl of single_port_rom is

  -- Build a 2-D array type for the RoM
  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

  function init_rom
    return memory_t is 
    variable tmp : memory_t := (others => (others => '0'));
  begin
    for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
      -- Initialize each address with the address itself
      tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
    end loop;
    return tmp;
  end init_rom;

  -- Declare the ROM signal and specify a default value.  Quartus II
  -- will create a memory initialization file (.mif) based on the 
  -- default value.
  signal rom : memory_t := init_rom;

begin

  process(clk)
  begin
    if(rising_edge(clk)) then
      q <= rom(addr);
    end if;
  end process;

end rtl;

--------------------------------------------------------------
-- 32*8 ROM module (ESD Book Chapter 5)
-- by Weijun Zhang, 04/2001
--
-- ROM model has predefined content for read only purpose
--------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ROM is
  port( Clock : in std_logic;
    Reset    : in std_logic;
    Enable   : in std_logic;
    Read     : in std_logic;
    Address  : in std_logic_vector(4 downto 0);
    Data_out : out std_logic_vector(7 downto 0)
  );
end ROM;

--------------------------------------------------------------

architecture Behav of ROM is

  type ROM_Array is array (0 to 31)
of std_logic_vector(7 downto 0);

  constant Content : ROM_Array := (
    0      => "00000001",   -- Suppose ROM has
    1      => "00000010",   -- prestored value
    2      => "00000011",   -- like this table
    3      => "00000100", --
    4      => "00000101",   --
    5      => "00000110", --
    6      => "00000111",   --
    7      => "00001000", --
    8      => "00001001", --
    9      => "00001010", --
    10     => "00001011",  --
    11     => "00001100", --
    12     => "00001101", --
    13     => "00001110",  --
    14     => "00001111",  --
    others => "11111111"   --
  );

begin
  process(Clock, Reset, Read, Address)
  begin
    if( Reset = '1' ) then
      Data_out <= "ZZZZZZZZ";
    elsif( Clock'event and Clock = '1' ) then
      if Enable = '1' then
        if( Read = '1' ) then
          Data_out <= Content(conv_integer(Address));
        else
          Data_out <= "ZZZZZZZZ";
        end if;
      end if;
    end if;
  end process;
end Behav;

 

       when "1011" => data <= my_rom(11);
       when "1100" => data <= my_rom(12);
       when "1101" => data <= my_rom(13);
       when "1110" => data <= my_rom(14);
       when "1111" => data <= my_rom(15);
       when others => data <= "00000000";
     end case;
  end process;
end architecture behavioral;

 

  process(clk)
  begin
    if(rising_edge(clk)) then
      q <= rom(addr);
    end if;
  end process;

end rtl;