1 -- 'Bucket Brigade' FIFO
2 -- 16 deep
3 -- 8-bit data
4 --
5 -- Version : 1.10
6 -- Version Date : 3rd December 2003
7 -- Reason : '--translate' directives changed to '--synthesis translate' directives
8 --
9 -- Version : 1.00
10 -- Version Date : 14th October 2002
11 --
12 -- Start of design entry : 14th October 2002
13 --
14 -- Ken Chapman
15 -- Xilinx Ltd
16 -- Benchmark House
17 -- 203 Brooklands Road
18 -- Weybridge
19 -- Surrey KT13 ORH
20 -- United Kingdom
21 --
22 -- chapman@xilinx.com
23 --
24 ------------------------------------------------------------------------------------
25 --
26 -- NOTICE:
27 --
28 -- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
29 -- third parties. By providing this core as one possible implementation of a standard,
30 -- Xilinx is making no representation that the provided implementation of this standard
31 -- is free from any claims of infringement by any third party. Xilinx expressly
32 -- disclaims any warranty with respect to the adequacy of the implementation, including
33 -- but not limited to any warranty or representation that the implementation is free
34 -- from claims of any third party. Futhermore, Xilinx is providing this core as a
35 -- courtesy to you and suggests that you contact all third parties to obtain the
36 -- necessary rights to use this implementation.
37 --
38 ------------------------------------------------------------------------------------
39 --
40 -- Library declarations
41 --
42 -- The Unisim Library is used to define Xilinx primitives. It is also used during
43 -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
44 --
45 ------------------------------------------------------------------------------------
46
47 library IEEE;
48 use IEEE.STD_LOGIC_1164.all;
49 use IEEE.STD_LOGIC_ARITH.all;
50 use IEEE.STD_LOGIC_UNSIGNED.all;
51 library unisim;
52 use unisim.vcomponents.all;
53
54 entity bbfifo_comp is
55 generic ( C_DWIDTH : positive := 8);
56 port (
57 i_reset : in std_logic;
58 i_clock : in std_logic;
59 i_fifo_wr : in std_logic;
60 i_fifo_rd : in std_logic;
61 o_fifo_full : out std_logic;
62 o_fifo_half_full : out std_logic;
63 o_fifo_data_present : out std_logic;
64 i_fifo_wdata : in std_logic_vector(C_DWIDTH-1 downto 0);
65 o_fifo_rdata : out std_logic_vector(C_DWIDTH-1 downto 0));
66 end bbfifo_comp;
67
68 architecture low_level_definition of bbfifo_comp is
69
70 signal pointer : std_logic_vector(3 downto 0);
71 signal next_count : std_logic_vector(3 downto 0);
72 signal half_count : std_logic_vector(3 downto 0);
73 signal count_carry : std_logic_vector(2 downto 0);
74 signal pointer_zero : std_logic;
75 signal pointer_full : std_logic;
76 signal decode_data_present : std_logic;
77 signal data_present_int : std_logic;
78 signal valid_write : std_logic;
79
80 ------------------------------------------------------------------------------------
81 -- Attributes to define LUT contents during implementation
82 -- The information is repeated in the generic map for functional simulation--
83 ------------------------------------------------------------------------------------
84 attribute INIT : string;
85 attribute INIT of zero_lut : label is "0001";
86 attribute INIT of full_lut : label is "8000";
87 attribute INIT of dp_lut : label is "BFA0";
88 attribute INIT of valid_lut : label is "C4";
89
90 begin
91
92 data_width_loop : for i in 0 to C_DWIDTH-1 generate
93 attribute INIT : string;
94 attribute INIT of data_srl : label is "0000";
95 begin
96 data_srl : SRL16E
97 --synthesis translate_off
98 generic map (INIT => X"0000")
99 --synthesis translate_on
100 port map(
101 D => i_fifo_wdata(i),
102 CE => valid_write,
103 CLK => i_clock,
104 A0 => pointer(0),
105 A1 => pointer(1),
106 A2 => pointer(2),
107 A3 => pointer(3),
108 Q => o_fifo_rdata(i) );
109 end generate data_width_loop;
110
111 -- 4-bit counter to act as data pointer
112 -- Counter is clock enabled by 'o_fifo_data_present'
113 -- Counter will be i_reset when 'i_reset' is active
114 -- Counter will increment when 'valid_write' is active
115 count_width_loop : for i in 0 to 3 generate
116 attribute INIT : string;
117 attribute INIT of count_lut : label is "6606";
118 begin
119 register_bit : FDRE
120 port map (
121 D => next_count(i),
122 Q => pointer(i),
123 CE => data_present_int,
124 R => i_reset,
125 C => i_clock);
126
127 count_lut : LUT4
128 --synthesis translate_off
129 generic map (INIT => X"6606")
130 --synthesis translate_on
131 port map(
132 I0 => pointer(i),
133 I1 => i_fifo_rd,
134 I2 => pointer_zero,
135 I3 => i_fifo_wr,
136 O => half_count(i));
137
138 lsb_count : if i = 0 generate
139 begin
140
141 count_muxcy : MUXCY
142 port map(
143 DI => pointer(i),
144 CI => valid_write,
145 S => half_count(i),
146 O => count_carry(i));
147
148 count_xor : XORCY
149 port map(
150 LI => half_count(i),
151 CI => valid_write,
152 O => next_count(i));
153
154 end generate lsb_count;
155
156 mid_count : if i > 0 and i < 3 generate
157 begin
158
159 count_muxcy : MUXCY
160 port map(
161 DI => pointer(i),
162 CI => count_carry(i-1),
163 S => half_count(i),
164 O => count_carry(i));
165
166 count_xor : XORCY
167 port map(
168 LI => half_count(i),
169 CI => count_carry(i-1),
170 O => next_count(i));
171
172 end generate mid_count;
173
174 upper_count : if i = 3 generate
175 begin
176
177 count_xor : XORCY
178 port map(
179 LI => half_count(i),
180 CI => count_carry(i-1),
181 O => next_count(i));
182
183 end generate upper_count;
184
185 end generate count_width_loop;
186
187
188 -- Detect when pointer is zero and maximum
189 zero_lut : LUT4
190 --synthesis translate_off
191 generic map (INIT => X"0001")
192 --synthesis translate_on
193 port map(
194 I0 => pointer(0),
195 I1 => pointer(1),
196 I2 => pointer(2),
197 I3 => pointer(3),
198 O => pointer_zero );
199
200
201 full_lut : LUT4
202 --synthesis translate_off
203 generic map (INIT => X"8000")
204 --synthesis translate_on
205 port map(
206 I0 => pointer(0),
207 I1 => pointer(1),
208 I2 => pointer(2),
209 I3 => pointer(3),
210 O => pointer_full );
211
212
213 -- Data Present status
214 dp_lut : LUT4
215 --synthesis translate_off
216 generic map (INIT => X"BFA0")
217 --synthesis translate_on
218 port map(
219 I0 => i_fifo_wr,
220 I1 => i_fifo_rd,
221 I2 => pointer_zero,
222 I3 => data_present_int,
223 O => decode_data_present );
224
225 dp_flop : FDR
226 port map (
227 D => decode_data_present,
228 Q => data_present_int,
229 R => i_reset,
230 C => i_clock);
231
232 -- Valid i_fifo_wr signal
233
234 valid_lut : LUT3
235 --synthesis translate_off
236 generic map (INIT => X"C4")
237 --synthesis translate_on
238 port map(
239 I0 => pointer_full,
240 I1 => i_fifo_wr,
241 I2 => i_fifo_rd,
242 O => valid_write );
243
244 -- assign internal signals to outputs
245 o_fifo_full <= pointer_full;
246 o_fifo_half_full <= pointer( 3 );
247 o_fifo_data_present <= data_present_int;
248
249 end low_level_definition;
250
251 library IEEE;
252 use IEEE.STD_LOGIC_1164.all;
253
254 -- Uncomment the following library declaration if using
255 -- arithmetic functions with Signed or Unsigned values
256 use IEEE.NUMERIC_STD.all;
257
258 -- Uncomment the following library declaration if instantiating
259 -- any Xilinx primitives in this code.
260 --library UNISIM;
261 --use UNISIM.VComponents.all;
262
263 entity bbfifo is
264 generic (
265 C_DWIDTH : positive := 8;
266 C_STAGE : positive := 6);
267 port (
268 i_reset : in std_logic;
269 i_clock : in std_logic;
270 i_fifo_wr : in std_logic;
271 i_fifo_rd : in std_logic;
272 i_fifo_wdata : in std_logic_vector(C_DWIDTH-1 downto 0);
273 o_fifo_rdata : out std_logic_vector(C_DWIDTH-1 downto 0);
274 o_fifo_full : out std_logic;
275 o_fifo_half_full : out std_logic;
276 o_fifo_data_present : out std_logic);
277 end bbfifo;
278
279 architecture Behavioral of bbfifo is
280
281 type fifo_data_type is array (C_STAGE downto 1) of std_logic_vector (C_DWIDTH-1 downto 0);
282 signal fifo_wdata : fifo_data_type;
283 signal fifo_rdata : fifo_data_type;
284 signal fifo_full : std_logic_vector(C_STAGE downto 1);
285 signal fifo_half_full : std_logic_vector(C_STAGE downto 1);
286 signal fifo_data_present : std_logic_vector(C_STAGE downto 1);
287 signal fifo_write : std_logic_vector(C_STAGE downto 1);
288 signal fifo_read : std_logic_vector(C_STAGE downto 1);
289
290 component bbfifo_comp
291 generic ( C_DWIDTH : positive := 8);
292 port (
293 i_reset : in std_logic;
294 i_clock : in std_logic;
295 i_fifo_wr : in std_logic;
296 i_fifo_rd : in std_logic;
297 o_fifo_full : out std_logic;
298 o_fifo_half_full : out std_logic;
299 o_fifo_data_present : out std_logic;
300 i_fifo_wdata : in std_logic_vector(C_DWIDTH-1 downto 0);
301 o_fifo_rdata : out std_logic_vector(C_DWIDTH-1 downto 0));
302 end component;
303
304 begin
305
306 o_fifo_full <= fifo_full(1);
307 o_fifo_rdata <= fifo_rdata(C_STAGE);
308 o_fifo_data_present <= fifo_data_present(C_STAGE);
309 o_fifo_half_full <= fifo_half_full((C_STAGE+1)/2) when C_STAGE rem 2 = 1 else
310 fifo_full( (C_STAGE+2) / 2 ); -- C_STAGE rem 2 = 0
311
312 G : for i in 1 to C_STAGE generate
313
314 bbfifo_comp_x : bbfifo_comp
315 generic map (
316 C_DWIDTH => C_DWIDTH )
317 port map (
318 i_reset => i_reset,
319 i_clock => i_clock,
320 i_fifo_wr => fifo_write(i),
321 i_fifo_rd => fifo_read(i),
322 o_fifo_full => fifo_full(i),
323 o_fifo_half_full => fifo_half_full(i),
324 o_fifo_data_present => fifo_data_present(i),
325 i_fifo_wdata => fifo_wdata(i),
326 o_fifo_rdata => fifo_rdata(i)
327 );
328
329 fifo_write_G1 : if i = 1 generate
330 fifo_write(1) <= i_fifo_wr;
331 fifo_wdata(1) <= i_fifo_wdata;
332 end generate fifo_write_G1;
333
334 -- Stage n is written when there is data in stage n-1 and stage n is not full.
335 -- This transfer of data also results in the corresponding read from stage n-1.
336 -- The transfer control signal is a single cycle pulse
337 -- to give time for the data present output of stage n-1
338 -- to respond to read event and go Low if possible.
339 fifo_write_Gx : if i > 1 generate
340 fifo_wdata(i) <= fifo_rdata(i-1);
341 process ( i_clock )
342 begin
343 if rising_edge( i_clock ) then
344 fifo_write(i) <= fifo_data_present(i-1) and not fifo_full(i) and not fifo_write(i);
345 end if;
346 end process;
347 end generate fifo_write_Gx;
348
349 fifo_read_Gn : if i = C_STAGE generate
350 fifo_read(C_STAGE) <= i_fifo_rd;
351 end generate fifo_read_Gn;
352
353 fifo_read_Gx : if i < C_STAGE generate
354 fifo_read(i) <= fifo_write(i+1);
355 end generate fifo_read_Gx;
356
357 end generate G;
358
359 end Behavioral;
View Code
