双端口RAM--verilog实现

双端口RAM 8bit*16

module test (
    input clka,
    input clkb,
    input rst,
    input w_en,
    input r_en,
    input [3:0]w_addr,
    input [3:0]r_addr,
    input [7:0]w_data,
    output reg [7:0]r_data
);
    integer i;
    reg [7:0]mem[15:0];
    always @(posedge clka) begin
        if(!rst) begin
            for ( i = 0; i<15 ; i=i+1 ) begin
                mem[i] <='b0;
            end
        end
    end
    always @(posedge clkb or negedge rst) begin
        if(!rst) begin
            r_data <= 'b0;
        end
        else if (w_en == 1'b0 && r_en == 1'b1) begin
            r_data <= mem[r_addr];
        end
        else begin
            r_data <= r_data;
        end
    end
    always @(posedge clka) begin
        if(w_en == 1'b1 && r_en == 1'b0) begin
            mem[w_addr] <= w_data;
        end
    end
endmodule

`timescale 1ns/1ps
module test_tb;
    reg clk;
    reg rst;
    reg w_en;
    reg r_en;
    reg [3:0]w_addr;
    reg [3:0]r_addr;
    reg [7:0]w_data;
    wire [7:0]r_data;

    test u1(
    .clka(clk),
    .clkb(clk),
    .rst(rst),
    .w_en(w_en),
    .r_en(r_en),
    .w_addr(w_addr),
    .r_addr(r_addr),
    .w_data(w_data),
    .r_data(r_data)
    );
    initial begin
        clk = 'b1;
        rst = 'b0;
        w_en = 'b0;
        r_en = 'b0;
        w_addr = 'b0;
        r_addr = 'b0;
        w_data = 'b0;
        #6;
        rst = 'b1;
    end
    always #5 clk = ~clk;
    initial begin
        #10;
        repeat(10) begin
            w_data = w_data + 1'b1;
            #10;
        end
    end
    initial begin
        #10;
        repeat(10) begin
            w_addr = w_addr + 1'b1;
            #10;
        end
        repeat(10) begin
            r_addr = r_addr + 1'b1;
            #10;
        end
    end
    initial begin
        w_en = 'b1;
        #110;
        r_en = 'b1;
        w_en = 'b0;
        #110;
        r_en = 'b0;
        w_en = 'b0;
        #40;
    end
endmodule