状态机相关知识点（2)--序列检测器1100101

上篇文章中最后使用moore状态机进行编码，今天这篇文章使用mealy状态机编码方式进行，对比结果及编码方式，状态转移图，会发现很多不同的地方。

mealy二段式状态机：状态转移图

 

 

 

相比moore状态机，mealy状态机的状态在这里是少一个，在其他可能会少很多。

主程序：

module sequence_fsm_mealy (
    clk,rst,d_in,d_out
);
    input clk;
    input rst;
    input d_in;
    output d_out;

    reg d_out;

    parameter s0 = 3'b000;
    parameter s1 = 3'b001;
    parameter s2 = 3'b010;
    parameter s3 = 3'b011;
    parameter s4 = 3'b100;
    parameter s5 = 3'b101;
    parameter s6 = 3'b110;

    reg [3:0]state,nextstate;

    always @(posedge clk or negedge rst) begin
        if(!rst) begin
            state <= s0;
        end
        else begin
            state <= nextstate;
        end
    end

    always @(state or d_in) begin
        d_out = 1'b0;
        nextstate = 3'bxxx;
        case(state)
        s0: begin
            if(d_in == 1'b0) begin
                d_out = 1'b0;
                nextstate = s0;
            end
            else begin
                d_out = 1'b0;
                nextstate = s1;
            end
        end
        s1: begin
            if(d_in == 1'b0) begin
                nextstate = s0;
            end
            else begin
                nextstate = s2;
                d_out = 1'b0;
            end
        end
        s2: begin
            if(d_in == 1'b0) begin
                nextstate = s3;
                d_out = 1'b0;
            end
            else begin
                nextstate = s2;
            end
        end
        s3: begin
            if (d_in == 1'b0) begin
                nextstate = s4;
                d_out = 1'b0;
            end
            else begin
                nextstate = s1;
                d_out = 1'b0;
            end
        end
        s4: begin
            if (d_in == 1'b0) begin
                nextstate = s0;
                d_out = 1'b0;
            end
            else begin
                nextstate = s5;
                d_out = 1'b0;
            end
        end
        s5: begin
            if (d_in == 1'b0) begin
                nextstate = s6;
                d_out = 1'b0;
            end
            else begin
                nextstate = s2;
                d_out = 1'b0;
            end
        end
        s6: begin
            if (d_in == 1'b0) begin
                nextstate = s0;
                d_out = 1'b0;
            end
            else begin
                nextstate = s1;
                d_out = 1'b1;
            end
        end
        default: begin
                nextstate = s0;
                d_out = 1'b0;
        endcase
    end
endmodule

tb：

`timescale 1ns/1ps
module sequence_fsm_mealy_tb;
    
    reg clk;
    reg rst;
    reg d_in;
    wire d_out;

    sequence_fsm_mealy u1(
    .clk(clk),
    .rst(rst),
    .d_in(d_in),
    .d_out(d_out)
);

initial begin
    clk = 1'b1;
    rst = 1'b0;
    #10;
    rst = 1'b1;
end

always #5 clk = ~clk;

initial begin
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 1;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     #10 d_in = 0;
     $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
     forever #10 begin
        d_in = {$random}%2;
        $display("display:simulation time is : %t",$time,"the value is :%b",d_in);
    end
end
endmodule

 

 输出跟输入有关，为即时输出。

二段式输出与三段式输出区别在与，三段的输出结果单独作为一个部分，二段的输出结果直接与组合逻辑融合。