K60——寄存器
（1）PTx_BASE_PTR为GPIO寄存器结构体基址指针(PTR即point to register，x=A/B/C/D/E)
/* GPIO - Peripheral instance base addresses */
/** Peripheral PTA base pointer */
#define PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u)//将32位值（内存地址）强制转换为结构体类型指针，即得到一个初始地址（基址）为0x400FF000u的GPIO_MemMapPtr结构体。
#define PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u)//将32位值（内存地址）强制转换为结构体类型指针，即得到一个初始地址（基址）为0x400FF000u的GPIO_MemMapPtr结构体。
/** Peripheral PTB base pointer */
#define PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u)
/** Peripheral PTC base pointer */
#define PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u)
/** Peripheral PTD base pointer */
#define PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u)
/** Peripheral PTE base pointer */
#define PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u)
#define PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u)
/** Peripheral PTC base pointer */
#define PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u)
/** Peripheral PTD base pointer */
#define PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u)
/** Peripheral PTE base pointer */
#define PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u)
//五个宏定义分别指向ABCDE口的GPIO寄存器结构体（每口有6个GPIO寄存器）
（2）GPIO寄存器结构体：嵌入式系统原理与实践（47页）
typedef struct GPIO_MemMap {
uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} volatile *GPIO_MemMapPtr;
uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} volatile *GPIO_MemMapPtr;
（3）调用GPIO寄存器结构体中的成员，即各种功能的寄存器，其中base为基址（对应（2））
/* GPIO - Register accessors */
#define GPIO_PDOR_REG(base) ((base)->PDOR)
#define GPIO_PSOR_REG(base) ((base)->PSOR)
#define GPIO_PCOR_REG(base) ((base)->PCOR)
#define GPIO_PTOR_REG(base) ((base)->PTOR)
#define GPIO_PDIR_REG(base) ((base)->PDIR)
#define GPIO_PDDR_REG(base) ((base)->PDDR)
#define GPIO_PDOR_REG(base) ((base)->PDOR)
#define GPIO_PSOR_REG(base) ((base)->PSOR)
#define GPIO_PCOR_REG(base) ((base)->PCOR)
#define GPIO_PTOR_REG(base) ((base)->PTOR)
#define GPIO_PDIR_REG(base) ((base)->PDIR)
#define GPIO_PDDR_REG(base) ((base)->PDDR)
（4）PORTx_BASE_PTR为内存映射结构体基址(PTR即point to register，x=A/B/C/D/E)
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base pointer */
#define PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u)
/** Peripheral PORTB base pointer */
#define PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u)
/** Peripheral PORTC base pointer */
#define PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u)
/** Peripheral PORTD base pointer */
#define PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u)
/** Peripheral PORTE base pointer */
#define PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u)
/** Peripheral PORTA base pointer */
#define PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u)
/** Peripheral PORTB base pointer */
#define PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u)
/** Peripheral PORTC base pointer */
#define PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u)
/** Peripheral PORTD base pointer */
#define PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u)
/** Peripheral PORTE base pointer */
#define PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u)
（5）内存映射结构体（注：查看K60数据手册K60P144M100SF2RM(Rev.6-2011.11)257页与264页）
/** PORT - Peripheral register structure */
typedef struct PORT_MemMap {
uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */引脚控制寄存器
uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} volatile *PORT_MemMapPtr;
typedef struct PORT_MemMap {
uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */引脚控制寄存器
uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} volatile *PORT_MemMapPtr;
注：以上结构体中定义了一系列寄存器，如引脚控制寄存器等，下面我们看如何调用这些寄存器，看下面的宏定义。
（6）调用内存映射结构体中的成员，即各种功能的寄存器，其中base为基址（对应（4）），对于引脚控制寄存器PCR来说，index为引脚号，即某端口的第几个引脚（内存上理解相当于偏移地址（offset））
#define PORT_PCR_REG(base,index) ((base)->PCR[index]) //引脚控制寄存器（PCR）
#define PORT_GPCLR_REG(base) ((base)->GPCLR)
#define PORT_GPCHR_REG(base) ((base)->GPCHR)
#define PORT_ISFR_REG(base) ((base)->ISFR)
#define PORT_DFER_REG(base) ((base)->DFER)
#define PORT_DFCR_REG(base) ((base)->DFCR)
#define PORT_DFWR_REG(base) ((base)->DFWR)
#define PORT_GPCHR_REG(base) ((base)->GPCHR)
#define PORT_ISFR_REG(base) ((base)->ISFR)
#define PORT_DFER_REG(base) ((base)->DFER)
#define PORT_DFCR_REG(base) ((base)->DFCR)
#define PORT_DFWR_REG(base) ((base)->DFWR)
(7)更改PCR寄存器指定位的值
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
