1 //date :2013/6/11
2 //designer :pengxiaoen
3 //function :serial_to_parallel
4
5 module serial_to_parallel (
6 clk_sp,reset_sp,
7 status_sp, // 1:out of the data. 0 : waiting
8 serial_in,
9 parallel_out,
10 );
11
12 input clk_sp,reset_sp;
13 input status_sp;
14 input serial_in;
15 output [7:0] parallel_out;
16
17 reg [7:0] parallel_reg;
18 always @ (posedge clk_sp or negedge reset_sp)
19 if (!reset_sp)
20 parallel_reg <= 8'd0;
21 else
22 parallel_reg <= {parallel_reg ,serial_in};
23
24 assign parallel_out = (status_sp) ? parallel_reg : 8'd0;
25
26 endmodule
