Five Key Changes Coming With DDR5 DIMMs
https://semiengineering.com/five-key-changes-coming-with-ddr5-dimms/
On July 14th of last year, JEDEC announced the publication of the DDR5 SDRAM standard. This signaled the nearing industry transition to DDR5 server dual-inline memory modules (DIMM). DDR5 memory brings a number of key enhancements that will bring great performance and power benefits in next generation servers.
Scaling Data Rates to 6.4 Gb/s
You can never have enough memory bandwidth, and DDR5 helps feed that insatiable need for speed. While DDR4 DIMMs top out at 3.2 gigabits per second (Gb/s) at a clock rate of 1.6 gigahertz (GHz), initial DDR5 will deliver a 50% bandwidth increase to 4.8 Gbps. DDR5 memory will ultimately double the data rate of DDR4 DRAM reaching 6.4 Gbps. New features, such as Decision Feedback Equalization (DFE), were incorporated in DDR5 enabling the higher IO speeds.
Lower Voltage Means Lower Power
A second major change is a reduction in operating voltage (VDD), and that will translate to lower power. With DDR5, the DRAM, buffer chip registering clock driver (RCD), and data buffer (DB) voltage drops from 1.2 V down to 1.1 V. However, lower VDD means smaller margin for noise immunity which designers will have to be cognizant of for their implementations.
New Power Architecture
A third change, and a major one, is power architecture. With DDR5 DIMMs, power management moves from the motherboard to the DIMM itself. DDR5 DIMMs will have a 12-V power management IC (PMIC) on DIMM allowing for better granularity of system power loading. The PMIC distributes the 1.1 V VDD supply, helping with signal integrity and noise with better on-DIMM control of the power supply.
Channel Architecture Update
Another major change with DDR5 is a new DIMM channel architecture. DDR4 DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels. Each of these channels will be 40-bits wide: 32 data bits with eight ECC bits. While the data width is the same (64-bits total) having two smaller independent channels improves memory access efficiency. In addition, DDR5 incorporates a fine grain bank refresh feature which allows some banks to refresh while others are in use. This has the further benefit of lowering latency. So not only do you get the benefit of the speed bump with DDR5, the benefit of that higher data rate is amplified by greater efficiency.
In the DDR5 DIMM architecture, the left and right side of the DIMM, each served by an independent 40-bit wide channel, share the RCD. In DDR4, the RCD provides two output clocks per side. In DDR5, the RCD provides four output clocks per side. In the highest density DIMMs with x4 DRAMs, this allows each group of 5 DRAMs (single rank, half-channel) to receive its own independent clock. Giving each rank and half-channel an independent clock improves signal integrity, helping to address the lower noise margin issue raised by lowering the VDD.
Higher Capacity
A fifth and final change to highlight is DDR5’s support for higher capacity DRAM devices. With DDR5 buffer chip DIMMs, the server or system designer can use densities of up to 64 Gb DRAMs in a single-die package. DDR4 maxes out at 16 Gb DRAM in a single-die package (SDP). DDR5 supports features like on-die ECC, error transparency mode, post-package repair, and read and write CRC modes to support higher-capacity DRAMs. The impact of higher capacity devices obviously translates to higher capacity DIMMs. So, while DDR4 DIMMs can have capacities of up to 64 GB (using SDP), DDR5 SDP-based DIMMs quadruple that to 256 GB.
Bringing It All Together
With the significant improvements and optimizations DDR5 offers over its DDR4 predecessor, the new memory standard also introduces multiple design considerations related to higher speeds and lower voltages that raise a new round of signal integrity challenges. Fortunately, DDR5 data buffer chips from suppliers such as Rambus effectively reduce the load on the data bus, enabling the higher speed, higher capacity DRAMs on the DIMM without degrading latency performance.
