TriBoard-TC1782翻译

FPC:Filter and Prescaler Cell

21.3.4 Input/Output Line Sharing Block (IOLS)

输入/输出线共享块
The I/O Line Sharing Block allows the 56 inputs and 112 outputs of the GPTA®v5 units
to be routed with high flexibility between I/O lines, output lines, clock inputs, other on-
chip peripherals and other GPTA®v5 cells. The GPTA®v5 module provides a total of 56
input lines and 112 output lines, assigned to seven I/O groups IOG[6:0], two on-chip
trigger and gating signal groups OTG[1:0], and seven output groups OG[6:0].

I / O线共享块允许GPTA®v5单元的56个输入和112个输出在I / O线，输出线，时钟输入，其他片上外设和其他GPTA®v5单元之间具有高灵活性。GPTA®v5模块提供总共56条输入线和112条输出线，分配给7个IOG [6：0] I / O组，片上触发和门控信号组OTG [1：0]和7个输出 组OG [6：0]。

The I/O Line Sharing Block does the following selections:
• FPC input line selection
• GTC and LTC output multiplexer selection
• On-chip trigger and gating signal selection
• GTC input multiplexer selection
• LTC input multiplexer selection

I / O线共享块执行以下选择：FPC输入线选择，GTC和LTC输出多路复用器选择，片上触发和门控信号选择，GTC输入多路复用器选择，LTC输入多路复用器选择。
For choosing these selection, the input and output lines of the related cells are integrated
into groups with eight parts each. Seven I/O groups, two on-chip and gating signal
groups, seven output groups, four GTC groups, eight LTC groups, one clock group, one
FPC/INT group, and one PDL/INT group are defined.

 为了选择这些选择，相关单元的输入和输出线被集成分成8组， 七个I / O组，两个片上和门控信组，七个产出组，四个GTC组，八个LTC组，一个时钟组，一个FPC / INT组和一个PDL / INT组。

An LTC group combines eight LTC cells with its input and output lines. This results in
eight LTC groups, LTCG0 to LTCG7.

LTC组合将八个LTC单元与其输入和输出线组合在一起。 8个LTC组，LTCG0至LTCG7
A GTC group combines eight GTC cells with its input and output lines. This results in
four GTC groups, GTCG0 to GTCG3.

GTC组合将八个GTC单元与其输入和输出线相结合。 我们的GTC组，GTCG0到GTCG3。

An I/O group combines eight GPTA®v5 I/O lines connected to bi-directional device pins
with its input and output lines. This results in seven I/O groups, IOG0 to IOG6, supporting
56 I/O lines.

I / O组将八个连接到双向器件引脚的GPTA®v5I / O线与其输入和输出线相结合。 这导致7个IOG0组，IOG0到IOG6，支持56个I / O线。

An Output group combines eight GPTA®v5 output lines connected to device pins as anoutput. This results in seven output groups, OG0 to OG6, supporting 56 output lines.

输出组合将连接到设备引脚的八个GPTA®v5输出线作为输出。 七个输出组，OG0到OG6，支持56个输出线。

The Clock group is a group that combines the eight clock bus output signals CLK[7:0]
generated by the clock distribution cells.

时钟组是组合八个时钟总线输出信号CLK [7：0]由时钟分配单元产生。

The FPC/INT group is a group that combines the six level output signals SOL[5:0] of the FPCs with two external input lines INT[1:0] of the GPTA®v5 unit.

FPC / INT组是将FPC的六电平输出信号SOL [5：0]与GPTA®v5单元的两个外部输入线INT [1：0]组合的组。
The PDL/INT group is a group that combines the four PDL output lines of the PDL bus
with four external input lines INT[3:0] of the GPTA®v5 unit.

PDL / INT组是组合PDL总线的四条PDL输出线的组与GPTA®v5单元的四个外部输入线INT [3：0]。

An On-chip trigger and gating signal group combines eight GPTA®v5 output lines
connected to on-chip peripherals. This results in two on-chip trigger and gating signal
groups, OTG0 to OG1, supporting 16 on-chip trigger and gating lines.

 

片内触发和门控信号组合组合了8个GPTA®v5输出线连接到片上外设。 这导致两个片上触发和门控信号组，OTG0至OG1，支持16个片内触发和选通线。

21.3.4.1 FPC Input Line Selection
As shown on Page 21-12, each FPC cell can be connected to one out of four input lines
SINk[3:0], to the GPTA®v5 module clock fGPTA, or to the output of the preceding FPC. In total, 24 input lines out of the 56 input lines IN[55:00] from the I/O groups are connected(not programmable) with the FPCk inputs. The FPCk input line selection is controlled by the FPCCTRk.IPS bit fields. Table 21-10 shows the FPC input line connections.

如图21-12所示，每个FPC单元可以连接到四个输入线SINk [3：0]中的一个，GPTA®v5模块时钟fGPTA或前一个FPC的输出。总共来自I / O组的56个输入线IN [55:00]中的24条输入线与FPCk输入端连接（不可编程）。FPCk输入线选择由FPCCTRk.IPS位字段控制。FPC输入线连接如表21-10所示。

 21.3.4.2 GTC and LTC Output Multiplexer Selection
The output multiplexer shown in Figure 21-64 and Figure 21-66 below connects the
32 GTC output lines and the 64 LTC output lines with the I/O groups (7 × 8 = 56 output
lines) and the output groups (7 × 8 = 56 output lines).
In case of low pin count packages, not all I/O groups may be routed to a pin.

The output multiplexer contains Output Multiplexer Groups (OMGs) that connect the
Global Timer Cells or Local Timer Cells with the input lines of the I/O groups and output
groups. GTCs and LTCs are grouped into four GTC groups (GTCG[3:0]) and eight LTC
groups (LTCG[7:0]) with 8 cells each. In the same way, I/O groups and output groups
are grouped into 14 groups (seven I/O groups and seven output groups) with 8 lines
each. IOG0 and OG0 share the same physical pins, similarly for IOG1 and OG1, IOG2
and OG2. IOG3 and IOG6 share the same physical pins for inputs as also outputs.

Rules for connections to Output Multiplexer Group OMG:
• Within a GTC or LTC group, the output of the cell with the lowest index number is
connected to OMG input line IN0. The remaining cells of a cell group are connected
to OMG input lines IN1 to IN7 with ascending cell index numbers.
Example: for OMG13 (see Figure 21-66), the cells LTC24 up to LTC31 are wired to
the OMG13 input lines IN0 to line IN7.
• OMG output line OUT0 is always connected to the input of an I/O or output group with
the lowest index. The remaining output lines OUT1 to OUT7 are connected to the I/O
or Output lines with ascending index.
Example: for OMG13 (see Figure 21-66), the outputs OUT0 to OUT7 are wired (via
OMG03) to input lines 0 to 7 of I/O group 3 (IOG3).
• One input of an I/O or output group can be connected to the output of only one timer
cell. This is guaranteed by the OMG control register layout. Otherwise, short circuits
and unpredictable behavior would occur. On the other hand, it is permissible for the
output of a GTC or LTC to be connected to more than one input of an I/O or output
group.
The output multiplexer group configuration is based on the following principles:
• Each OMG is referenced with two index variables: n and g (OMGng)
• Index n is a group number. Global timer cell groups GTCG[3:0] have the group
number 0, Local Timer Cell Groups LTCG[3:0] have the group number 1, and Local
Timer Cell Groups LTCG[7:4] have the group number 2.

• Index g indicates the number of an I/O or output group g (g = 0-13D) to which the
outputs of the output multiplexer group OMGng are connected. I/O groups IOG0 to
IOG6 are assigned to index variable g = 0 to 6 and output groups OG0 to OG6 are
assigned to index variable g = 7 to 13.

The output multiplexer logic as seen for programming is shown in Figure 21-68. With
this logic, always three GTC or LTC group signals are combined to one output line that
leads to the input of an I/O or output group. For example, when looking at Figure 21-66,
each of the eight output multiplexer output lines to I/O group IOG5 is connected via three
OMGn5 (n = 0, 1, 2) with  the eight outputs of one GTC group (GTCG1) and two LTC
groups (LTCG1 and LTCG5).

The 1. level multiplexer is built up by three 8:1 multiplexers that are controlled in parallel
by bit field OMLn. Bit field OMGn controls the 2. level multiplexer and connects one of
the 1. level multiplexer outputs to output n. The output of the 2. level multiplexer is
connected only to the input of an I/O group or output group if bit MRACTL.MAEN is set
(multiplexer array enabled) and no reserved bit combination of OMGn is selected. If one
of these conditions is not true, the corresponding OMG output will be held at a low level.
Two Output GPTA®v5, OMCRL and OMCRH (see also Page 21-121), are assigned to
each of the I/O or output groups. Therefore, a total of 28 registers control the
connections within the output multiplexer of the GPTA®v5 module.
The OMCRL registers control the OMG output lines 0 to 3. The OMCRH registers control
the OMG output lines 4 to 7. Table 21-11 lists all Output Multiplexer Control Registers
with its control functions. Please note that the Output Multiplexer Control Registers are

not directly accessible but must be written  or read using a FIFO array structure as
described on Page 21-121.