摘要：
串口(UART)DIV_VAL=(PCLK/(bpsx16))−135=115200/66.5/16-1查看芯片手册：GPACON0x7F008000R/WPortAConfigurationRegister0x0000GPA0[3:0]0000=Input0001=Output0010=UARTRXD[0]0011=Reserved0100=Reserved0101=Reserved0110=Reserved0111=ExternalInterruptGroup1[0]0000GPA1[7:4]0000=Input0001=Output0010=UARTTXD[0]0011=Reserved 阅读全文
摘要：
12m晶振----->pll------>cpuMux多路选择器Div分频器示例代码如下：汇编实现.globlclock_initclock_init:/*1.设置LOCK_TIME*/ldrr0,=0x7E00F000/*APLL_LOCK*/ldrr1,=0x0000FFFFstrr1,[r0]strr1,[r0,#4] /*MPLL_LOCK*/strr1,[r0,#8] /*EPLL_LOCK*/#defineOTHERS 0x7e00f900@setasyncmode/*当CPU时钟!=HCLK时，要设为异步模式*/ldrr0,=OTHERSldrr1,[r0]bicr1 阅读全文