从零开始的SystemVerilog之modelsim的仿真教程 Label: Research

合集 - FPGA(13)

1.keep_hierarchy约束在三模冗余中的应用2024-02-20 2.Libero SoC 如何导入模块Module2024-01-15 3.FPGA直方图均衡化2023-10-03 4.Microsemi Libero SoC使用教程（胎教级免费）（创建工程、引脚分配、仿真、逻辑分析仪ILA）2024-01-15 5.从零开始的zynq之petalinux胎教级安装教程2022-09-11

6.从零开始的SystemVerilog之modelsim的仿真教程 Label: Research2022-09-17

7.FPGA原语及IDDR仿真2024-03-27 8.常用时序收敛方法2024-03-28 9.FPGA时序约束步骤（vivado）2024-03-28 10.信号加扰与FPGA实现2024-07-05 11.AXI总线掩码（WSTRB）操作2024-07-23 12.FPGA DFT/FFT2024-10-18 13.DDR浅析2024-10-22

首先激活modelsim然后打开modelsim

新建project

选择要使用的语言，这里使用systemverilog

对于初学者，可以只使用一个文件编写主要模块和testbench（tb文件），所以这里直接关闭窗口

双击打开

填入测试代码

package definitions;
    parameter   version = "1.1";
     
    typedef enum {ADD, SUB, MUL} opcodes_t;
 
    typedef struct {
        logic   [31:0]  a, b;
        opcodes_t   opcode; //opcode ADD, SUB MUL
    } instruction_t;
 
    typedef union  {
        logic [31 : 0] u_data;
        logic signed [31 : 0] s_data;
    } data_t;
 
      
endpackage 
 
//import definitions::*;
 
module homework5_5(
//  import definitions:: instruction_t IW,
    input logic read,
    output logic [31:0] result);
     
    import definitions:: *;
     
    enum logic {ON=1'b0, OFF=1'b1, HZ=1'bz, UN=1'bx} fo_st;
     
endmodule
 
`timescale 1 ns/ 1 ns
module homework5_5_tb();
logic read;//tb这里不要写input和output
logic [31:0] result;
 
// assign statements (if any)                          
homework5_5 i1 (//注意这里的引用要和主模块名称一致
// port map - connection between master ports and signals/registers   
    .read(read),
    .result(result)
);
 
initial                                                
begin                                               
    read=0;
    result=0;
    $display("variable"); 
end
                                                     
always                                                    
begin                                                             
    #10;
    result++;
    read+=2;
    if ($time >= 1000) begin
        $finish ;
    end
end        
 
endmodule