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2017年2月10日

摘要： Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The tri0 and tri1 nets model nets with resistive pulldown and resistive 阅读全文

posted @ 2017-02-10 12:37 QIYUEXIN 阅读(970) 评论(0) 推荐(0) 编辑

9.3.1 The assign and deassign procedural statements

摘要： IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The assign procedural continuous assignment statement shall override all pro 阅读全文

posted @ 2017-02-10 11:25 QIYUEXIN 阅读(335) 评论(0) 推荐(0) 编辑

10. Tasks and functions

摘要： Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language 10. Tasks and functions Tasks and functions provide the ability to exec 阅读全文

posted @ 2017-02-10 09:28 QIYUEXIN 阅读(377) 评论(0) 推荐(0) 编辑

2017年2月9日

6.1.2 The continuous assignment statement

摘要： Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The continuous assignment statement shall place a continuous assignment 阅读全文

posted @ 2017-02-09 23:04 QIYUEXIN 阅读(503) 评论(0) 推荐(0) 编辑

Quartus II 使用 modelsim 仿真

摘要： Quartus II 使用 modelsim 仿真阅读全文

posted @ 2017-02-09 22:00 QIYUEXIN 阅读(16341) 评论(0) 推荐(1) 编辑

与DSP通信时，RD&WR信号

摘要： /////////////////////////////////////////////////////////// reg [ 1:0] rd,wr; reg [15:0] dsp_data_out; assign DSP_D = (DSP_WE && !DSP_RD) ? dsp_data_out:16'hzzzz; // Below is the communication... 阅读全文

posted @ 2017-02-09 15:46 QIYUEXIN 阅读(1091) 评论(0) 推荐(0) 编辑

4.2.1 Vector bit-select and part-select addressing

摘要： Frm:IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language Bit-selects extract a particular bit from a vector net, vector reg, inte 阅读全文

posted @ 2017-02-09 09:36 QIYUEXIN 阅读(1833) 评论(0) 推荐(0) 编辑