摘要：
/////////////////////////////////////////////////////////// reg [ 1:0] rd,wr; reg [15:0] dsp_data_out; assign DSP_D = (DSP_WE && !DSP_RD) ? dsp_data_out:16'hzzzz; // Below is the communication... 阅读全文
摘要：
Frm:IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language Bit-selects extract a particular bit from a vector net, vector reg, inte 阅读全文