2017年2月10日
9.3.2 The force and release procedural statements
摘要： Frm： IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language Another form of procedural continuous assignment is provided by the for 阅读全文
posted @ 2017-02-10 18:17 QIYUEXIN 阅读(299) 评论(0) 推荐(0) 编辑
3.7.4 Tri0 and tri1 nets
摘要： Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The tri0 and tri1 nets model nets with resistive pulldown and resistive 阅读全文
posted @ 2017-02-10 12:37 QIYUEXIN 阅读(970) 评论(0) 推荐(0) 编辑
9.3.1 The assign and deassign procedural statements
摘要： IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The assign procedural continuous assignment statement shall override all pro 阅读全文
posted @ 2017-02-10 11:25 QIYUEXIN 阅读(335) 评论(0) 推荐(0) 编辑
10. Tasks and functions
摘要： Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language 10. Tasks and functions Tasks and functions provide the ability to exec 阅读全文
posted @ 2017-02-10 09:28 QIYUEXIN 阅读(377) 评论(0) 推荐(0) 编辑